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Message-ID: <alpine.DEB.2.21.2306111611170.64925@angie.orcam.me.uk>
Date: Sun, 11 Jun 2023 18:19:57 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Bjorn Helgaas <bhelgaas@...gle.com>,
Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
Oliver O'Halloran <oohall@...il.com>,
Michael Ellerman <mpe@...erman.id.au>,
Nicholas Piggin <npiggin@...il.com>,
Christophe Leroy <christophe.leroy@...roup.eu>,
Saeed Mahameed <saeedm@...dia.com>,
Leon Romanovsky <leon@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>
cc: Alex Williamson <alex.williamson@...hat.com>,
Lukas Wunner <lukas@...ner.de>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Stefan Roese <sr@...x.de>, Jim Wilson <wilson@...iptree.org>,
David Abdurachmanov <david.abdurachmanov@...il.com>,
Pali Rohár <pali@...nel.org>,
linux-pci@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
linux-rdma@...r.kernel.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v9 11/14] PCI: Use `pcie_wait_for_link_status' in
`pcie_wait_for_link_delay'
Remove a DLLLA status bit polling loop from `pcie_wait_for_link_delay'
and call almost identical code in `pcie_wait_for_link_status' instead.
This reduces the lower bound on the polling interval from 10ms to 1ms,
possibly increasing the CPU load on the system in favour to reducing
the wait time.
Signed-off-by: Maciej W. Rozycki <macro@...am.me.uk>
---
New change in v9.
---
drivers/pci/pci.c | 17 +++--------------
1 file changed, 3 insertions(+), 14 deletions(-)
linux-pcie-wait-for-link-delay-status.diff
Index: linux-macro/drivers/pci/pci.c
===================================================================
--- linux-macro.orig/drivers/pci/pci.c
+++ linux-macro/drivers/pci/pci.c
@@ -4889,16 +4889,14 @@ static bool pcie_wait_for_link_status(st
static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
int delay)
{
- int timeout = PCIE_LINK_RETRAIN_TIMEOUT_MS;
bool ret;
- u16 lnk_status;
/*
* Some controllers might not implement link active reporting. In this
* case, we wait for 1000 ms + any delay requested by the caller.
*/
if (!pdev->link_active_reporting) {
- msleep(timeout + delay);
+ msleep(PCIE_LINK_RETRAIN_TIMEOUT_MS + delay);
return true;
}
@@ -4913,20 +4911,11 @@ static bool pcie_wait_for_link_delay(str
*/
if (active)
msleep(20);
- for (;;) {
- pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
- ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
- if (ret == active)
- break;
- if (timeout <= 0)
- break;
- msleep(10);
- timeout -= 10;
- }
+ ret = pcie_wait_for_link_status(pdev, false, active);
if (active && ret)
msleep(delay);
- return ret == active;
+ return ret;
}
/**
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