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Message-ID: <38c30778-9526-cba6-4ddb-00bcefeb5647@linaro.org>
Date: Mon, 12 Jun 2023 13:22:09 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Borislav Petkov <bp@...en8.de>, Marvin Lin <milkfafa@...il.com>
Cc: robh+dt@...nel.org, tony.luck@...el.com, james.morse@....com,
mchehab@...nel.org, rric@...nel.org, benjaminfair@...gle.com,
yuenn@...gle.com, venture@...gle.com, avifishman70@...il.com,
tmaimon77@...il.com, tali.perry1@...il.com,
linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, openbmc@...ts.ozlabs.org,
KWLIU@...oton.com, YSCHU@...oton.com, ctcchien@...oton.com,
kflin@...oton.com
Subject: Re: [PATCH v18 1/3] ARM: dts: nuvoton: Add node for NPCM memory
controller
On 12/06/2023 13:04, Borislav Petkov wrote:
> On Wed, Jan 11, 2023 at 05:32:43PM +0800, Marvin Lin wrote:
>> Add node for memory controller present on Nuvoton NPCM SoCs. The
>> memory controller supports single bit error correction and double bit
>> error detection.
>>
>> Signed-off-by: Marvin Lin <milkfafa@...il.com>
>> ---
>> arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
>> 1 file changed, 7 insertions(+)
>
> I guess this needs an Ack from OF folks if it is going to go through the
> EDAC tree ...
It is preferred this goes via Nuvoton ARM SoC tree. I don't understand
why this is first in the series - it's clearly wrong.
Best regards,
Krzysztof
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