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Message-ID: <1686570177-2836108-1-git-send-email-srinivas.goud@amd.com>
Date: Mon, 12 Jun 2023 17:12:54 +0530
From: Srinivas Goud <srinivas.goud@....com>
To: <wg@...ndegger.com>, <mkl@...gutronix.de>, <davem@...emloft.net>,
<edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>,
<gcnu.goud@...il.com>
CC: <git@....com>, <michal.simek@...inx.com>,
<linux-can@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
Srinivas Goud <srinivas.goud@....com>
Subject: [PATCH 0/3] can: xilinx_can: Add ECC feature support
ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller.
Part of this feature configuration and counter registers added
in Xilinx CAN Controller for 1bit/2bit ECC errors count and reset.
Please find more details in PG096 v5.1 document.
xlnx,has-ecc is optional property and added to Xilinx CAN Controller
node if ECC block enabled in the HW.
Driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupts
and also create debugfs entry for reading all the ECC errors.
Srinivas Goud (3):
dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’
can: xilinx_can: Add ECC support
can: xilinx_can: Add debugfs support for ECC
.../devicetree/bindings/net/can/xilinx,can.yaml | 5 +
drivers/net/can/xilinx_can.c | 169 ++++++++++++++++++++-
2 files changed, 169 insertions(+), 5 deletions(-)
--
2.1.1
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