linux-kernel - Re: [PATCH v3 1/8] PCI: qcom: Use DWC helpers for modifying the read-only DBI registers

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Date:   Mon, 12 Jun 2023 14:46:04 +0200
From:   Lorenzo Pieralisi <lpieralisi@...nel.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc:     kw@...ux.com, bhelgaas@...gle.com, robh@...nel.org,
        andersson@...nel.org, konrad.dybcio@...aro.org,
        linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, steev@...i.org,
        quic_srichara@...cinc.com,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v3 1/8] PCI: qcom: Use DWC helpers for modifying the
 read-only DBI registers

On Thu, Jun 01, 2023 at 10:08:53PM +0530, Manivannan Sadhasivam wrote:
> DWC core already exposes dw_pcie_dbi_ro_wr_{en/dis} helper APIs for
> enabling and disabling the write access to read only DBI registers. So
> let's use them instead of doing it manually.
> 
> Also, the existing code doesn't disable the write access when it's done.
> This is also fixed now.

I am afraid we need to split this up, sorry, it is two logical
changes (and of them is a fix AFAICS).

Lorenzo

> Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller")
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 4ab30892f6ef..01795ee7ce45 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -61,7 +61,6 @@
>  /* DBI registers */
>  #define AXI_MSTR_RESP_COMP_CTRL0		0x818
>  #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
> -#define MISC_CONTROL_1_REG			0x8bc
>  
>  /* MHI registers */
>  #define PARF_DEBUG_CNT_PM_LINKST_IN_L2		0xc04
> @@ -132,9 +131,6 @@
>  /* AXI_MSTR_RESP_COMP_CTRL1 register fields */
>  #define CFG_BRIDGE_SB_INIT			BIT(0)
>  
> -/* MISC_CONTROL_1_REG register fields */
> -#define DBI_RO_WR_EN				1
> -
>  /* PCI_EXP_SLTCAP register fields */
>  #define PCIE_CAP_SLOT_POWER_LIMIT_VAL		FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
>  #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
> @@ -826,7 +822,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
>  	writel(0, pcie->parf + PARF_Q2A_FLUSH);
>  
>  	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
> -	writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG);
> +
> +	dw_pcie_dbi_ro_wr_en(pci);
> +
>  	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>  
>  	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> @@ -836,6 +834,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
>  	writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
>  		PCI_EXP_DEVCTL2);
>  
> +	dw_pcie_dbi_ro_wr_dis(pci);
> +
>  	return 0;
>  }
>  
> -- 
> 2.25.1
>