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Message-Id: <20230613161034.3496047-4-michal.wilczynski@intel.com>
Date: Tue, 13 Jun 2023 19:10:32 +0300
From: Michal Wilczynski <michal.wilczynski@...el.com>
To: linux-acpi@...r.kernel.org
Cc: rafael@...nel.org, andriy.shevchenko@...el.com,
artem.bityutskiy@...ux.intel.com, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, hpa@...or.com, lenb@...nel.org,
jgross@...e.com, linux-kernel@...r.kernel.org, x86@...nel.org
Subject: [PATCH v3 3/5] acpi: Introduce new function callback for _OSC
Currently in ACPI code _OSC method is already used for workaround
introduced in commit a21211672c9a ("ACPI / processor: Request native
thermal interrupt handling via _OSC"). Create new function, similar to
already existing acpi_hwp_native_thermal_lvt_osc(). Call new function
acpi_processor_osc(). Make this function fulfill the purpose previously
fulfilled by the workaround plus convey OSPM processor capabilities
with it by setting correct processor capability bits.
Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@...el.com>
Signed-off-by: Michal Wilczynski <michal.wilczynski@...el.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
---
arch/x86/include/asm/acpi.h | 3 +++
drivers/acpi/acpi_processor.c | 43 ++++++++++++++++++++++++++++++++++-
include/acpi/pdc_intel.h | 1 +
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 6a498d1781e7..6c25ce2dad18 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -112,6 +112,9 @@ static inline void arch_acpi_set_proc_cap_bits(u32 *cap)
if (cpu_has(c, X86_FEATURE_ACPI))
*cap |= ACPI_PDC_T_FFH;
+ if (cpu_has(c, X86_FEATURE_HWP))
+ *cap |= ACPI_PDC_COLLAB_PROC_PERF;
+
/*
* If mwait/monitor is unsupported, C2/C3_FFH will be disabled
*/
diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c
index 8c5d0295a042..0de0b05b6f53 100644
--- a/drivers/acpi/acpi_processor.c
+++ b/drivers/acpi/acpi_processor.c
@@ -591,13 +591,54 @@ void __init processor_dmi_check(void)
dmi_check_system(processor_idle_dmi_table);
}
+/* vendor specific UUID indicating an Intel platform */
+static u8 sb_uuid_str[] = "4077A616-290C-47BE-9EBD-D87058713953";
static bool acpi_hwp_native_thermal_lvt_set;
+static acpi_status __init acpi_processor_osc(acpi_handle handle, u32 lvl,
+ void *context, void **rv)
+{
+ u32 capbuf[2] = {};
+ acpi_status status;
+ struct acpi_osc_context osc_context = {
+ .uuid_str = sb_uuid_str,
+ .rev = 1,
+ .cap.length = 8,
+ .cap.pointer = capbuf,
+ };
+
+ if (processor_physically_present(handle) == false)
+ return AE_OK;
+
+ arch_acpi_set_proc_cap_bits(&capbuf[OSC_SUPPORT_DWORD]);
+
+ if (boot_option_idle_override == IDLE_NOMWAIT)
+ capbuf[OSC_SUPPORT_DWORD] &=
+ ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH);
+
+ status = acpi_run_osc(handle, &osc_context);
+ if (ACPI_FAILURE(status))
+ return status;
+
+ if (osc_context.ret.pointer && osc_context.ret.length > 1) {
+ u32 *capbuf_ret = osc_context.ret.pointer;
+
+ if (!acpi_hwp_native_thermal_lvt_set &&
+ capbuf_ret[1] & ACPI_PDC_COLLAB_PROC_PERF) {
+ acpi_handle_info(handle,
+ "_OSC native thermal LVT Acked\n");
+ acpi_hwp_native_thermal_lvt_set = true;
+ }
+ }
+ kfree(osc_context.ret.pointer);
+
+ return AE_OK;
+}
+
static acpi_status __init acpi_hwp_native_thermal_lvt_osc(acpi_handle handle,
u32 lvl,
void *context,
void **rv)
{
- u8 sb_uuid_str[] = "4077A616-290C-47BE-9EBD-D87058713953";
u32 capbuf[2];
struct acpi_osc_context osc_context = {
.uuid_str = sb_uuid_str,
diff --git a/include/acpi/pdc_intel.h b/include/acpi/pdc_intel.h
index 967c552d1cd3..9427f639287f 100644
--- a/include/acpi/pdc_intel.h
+++ b/include/acpi/pdc_intel.h
@@ -16,6 +16,7 @@
#define ACPI_PDC_C_C1_FFH (0x0100)
#define ACPI_PDC_C_C2C3_FFH (0x0200)
#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
+#define ACPI_PDC_COLLAB_PROC_PERF (0x1000)
#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
ACPI_PDC_C_C1_HALT | \
--
2.41.0
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