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Message-ID: <20230613163936.ajlomb3xaqx52zhr@mercury.elektranox.org>
Date: Tue, 13 Jun 2023 18:39:36 +0200
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Sascha Hauer <s.hauer@...gutronix.de>
Cc: linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, Heiko Stuebner <heiko@...ech.de>,
Kyungmin Park <kyungmin.park@...sung.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>, kernel@...gutronix.de,
Michael Riesch <michael.riesch@...fvision.net>,
Robin Murphy <robin.murphy@....com>,
Vincent Legoll <vincent.legoll@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH v5 08/25] PM / devfreq: rk3399_dmc,dfi: generalize
DDRTYPE defines
Hi,
On Wed, May 24, 2023 at 10:31:36AM +0200, Sascha Hauer wrote:
> The DDRTYPE defines are named to be RK3399 specific, but they can be
> used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
> prefix with ROCKCHIP_. They are defined in a SoC specific header
> file, so when generalizing the prefix also move the new defines to
> a SoC agnostic header file. While at it use GENMASK to define the
> DDRTYPE bitfield and give it a name including the full register name.
>
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> ---
Reviewed-by: Sebastian Reichel <sebastian.reichel@...labora.com>
-- Sebastian
> drivers/devfreq/event/rockchip-dfi.c | 9 +++++----
> drivers/devfreq/rk3399_dmc.c | 10 +++++-----
> include/soc/rockchip/rk3399_grf.h | 7 +------
> include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++
> 4 files changed, 28 insertions(+), 15 deletions(-)
> create mode 100644 include/soc/rockchip/rockchip_grf.h
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 82de24a027579..6bccb6fbcfc0c 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -18,8 +18,10 @@
> #include <linux/list.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/bitfield.h>
> #include <linux/bits.h>
>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
>
> #define DMC_MAX_CHANNELS 2
> @@ -74,9 +76,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
> writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
>
> /* set ddr type to dfi */
> - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
> + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
> writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
> - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
> + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
> writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
>
> /* enable count, use software mode */
> @@ -191,8 +193,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
>
> /* get ddr type */
> regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> dfi->channel_mask = GENMASK(1, 0);
>
> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> index daff407026157..fd2c5ffedf41e 100644
> --- a/drivers/devfreq/rk3399_dmc.c
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -22,6 +22,7 @@
> #include <linux/suspend.h>
>
> #include <soc/rockchip/pm_domains.h>
> +#include <soc/rockchip/rockchip_grf.h>
> #include <soc/rockchip/rk3399_grf.h>
> #include <soc/rockchip/rockchip_sip.h>
>
> @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
> }
>
> regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
> - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
> - RK3399_PMUGRF_DDRTYPE_MASK;
> + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
>
> switch (ddr_type) {
> - case RK3399_PMUGRF_DDRTYPE_DDR3:
> + case ROCKCHIP_DDRTYPE_DDR3:
> data->odt_dis_freq = data->ddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR3:
> + case ROCKCHIP_DDRTYPE_LPDDR3:
> data->odt_dis_freq = data->lpddr3_odt_dis_freq;
> break;
> - case RK3399_PMUGRF_DDRTYPE_LPDDR4:
> + case ROCKCHIP_DDRTYPE_LPDDR4:
> data->odt_dis_freq = data->lpddr4_odt_dis_freq;
> break;
> default:
> diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h
> index 3eebabcb28123..775f8444bea8d 100644
> --- a/include/soc/rockchip/rk3399_grf.h
> +++ b/include/soc/rockchip/rk3399_grf.h
> @@ -11,11 +11,6 @@
>
> /* PMU GRF Registers */
> #define RK3399_PMUGRF_OS_REG2 0x308
> -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13
> -#define RK3399_PMUGRF_DDRTYPE_MASK 7
> -#define RK3399_PMUGRF_DDRTYPE_DDR3 3
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6
> -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7
> +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13)
>
> #endif
> diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h
> new file mode 100644
> index 0000000000000..dde1a9796ccb5
> --- /dev/null
> +++ b/include/soc/rockchip/rockchip_grf.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Rockchip General Register Files definitions
> + */
> +
> +#ifndef __SOC_ROCKCHIP_GRF_H
> +#define __SOC_ROCKCHIP_GRF_H
> +
> +/* Rockchip DDRTYPE defines */
> +enum {
> + ROCKCHIP_DDRTYPE_DDR3 = 3,
> + ROCKCHIP_DDRTYPE_LPDDR2 = 5,
> + ROCKCHIP_DDRTYPE_LPDDR3 = 6,
> + ROCKCHIP_DDRTYPE_LPDDR4 = 7,
> +};
> +
> +#endif /* __SOC_ROCKCHIP_GRF_H */
> --
> 2.39.2
>
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