linux-kernel - Re: [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node

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Message-ID: <20230613-ferret-sleeve-d0e4a5b2289e@spud>
Date:   Tue, 13 Jun 2023 20:55:45 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Conor Dooley <conor+dt@...nel.org>,
        Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Hal Feng <hal.feng@...rfivetech.com>,
        William Qiu <william.qiu@...rfivetech.com>,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock
 source in SYSCRG node

On Tue, Jun 13, 2023 at 08:58:52PM +0800, Xingyu Wu wrote:
> Modify the SYSCRG node to add PLL clocks input from
> PLL clocks driver.
> 
> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>

Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Cheers,
Conor.

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