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Message-ID: <CAL_JsqLMtf__1Q+5MiaoXXx1LO=49XG490HZxOxcD7yDveioiQ@mail.gmail.com>
Date: Tue, 13 Jun 2023 17:31:42 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Frank Li <Frank.Li@....com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>, imx@...ts.linux.dev
Subject: Re: [PATCH v2 1/1] arm64: dts: imx8mp: Add coresight trace components
On Mon, May 15, 2023 at 9:02 AM Frank Li <Frank.Li@....com> wrote:
>
> Add coresight trace components (ETM, ETF, ETB and Funnel).
>
> ┌───────┐ ┌───────┐ ┌───────┐
> │ CPU0 ├─►│ ETM0 ├─►│ │
> └───────┘ └───────┘ │ │
> │ │
> ┌───────┐ ┌───────┐ │ ATP │
> │ CPU1 ├─►│ ETM1 ├─►│ │
> └───────┘ └───────┘ │ │
> │ FUNNEL│
> ┌───────┐ ┌───────┐ │ │
> │ CPU2 ├─►│ ETM2 ├─►│ │
> └───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐
> │ │ │ │ │ │
> ┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │
> │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │
> └───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI
> │ │ │ ▲
> ▼ ▼ ▼ │
> ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐
> │ ATP FUNNEL ├──►│ETF ├─► │ETR │
> └───────────────────────────┘ └─────┘ └────┘
>
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
> Change from v1 to v2
> - add new line between nodes
> - add new line between properties and child node
>
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 204 ++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index a19224fe1a6a..1a25710c3a90 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -304,6 +304,210 @@ soc: soc@0 {
> nvmem-cells = <&imx8mp_uid>;
> nvmem-cell-names = "soc_unique_id";
>
> + etm0: etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x28440000 0x10000>;
> + arm,primecell-periphid = <0xbb95d>;
> + cpu = <&A53_0>;
> + clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etm0_out_port: endpoint {
> + remote-endpoint = <&ca_funnel_in_port0>;
> + };
> + };
> + };
> + };
> +
> + etm1: etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x28540000 0x10000>;
> + arm,primecell-periphid = <0xbb95d>;
> + cpu = <&A53_1>;
> + clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etm1_out_port: endpoint {
> + remote-endpoint = <&ca_funnel_in_port1>;
> + };
> + };
> + };
> + };
> +
> + etm2: etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x28640000 0x10000>;
> + arm,primecell-periphid = <0xbb95d>;
> + cpu = <&A53_2>;
> + clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etm2_out_port: endpoint {
> + remote-endpoint = <&ca_funnel_in_port2>;
> + };
> + };
> + };
> + };
> +
> + etm3: etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x28740000 0x10000>;
> + arm,primecell-periphid = <0xbb95d>;
> + cpu = <&A53_3>;
> + clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etm3_out_port: endpoint {
> + remote-endpoint = <&ca_funnel_in_port3>;
> + };
> + };
> + };
> + };
> +
> + funnel {
> + /*
> + * non-configurable funnel don't show up on the AMBA
> + * bus. As such no need to add "arm,primecell".
> + */
> + compatible = "arm,coresight-static-funnel";
This device has no registers so it should not be under the bus node.
This is pointed out by the dtschema checks. Please don't add new ones.
Rob
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