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Message-ID: <4fec9cf7-b4b6-c5c1-7db5-493240c54ef1@arm.com>
Date: Tue, 13 Jun 2023 09:31:13 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Mark Brown <broonie@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
Rob Herring <robh@...nel.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
James Morse <james.morse@....com>, kvmarm@...ts.linux.dev,
coresight@...ts.linaro.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 12/14] arm64/sysreg: Convert TRBMAR_EL1 register to
automatic generation
On 6/2/23 17:35, Mark Brown wrote:
> On Fri, Jun 02, 2023 at 11:55:50AM +0530, Anshuman Khandual wrote:
>
>> +Sysreg TRBMAR_EL1 3 0 9 11 4
>> +Res0 63:12
>> +Field 11:10 PAS
>> +Field 9:8 SH
>> +Field 7:0 Attr
>> +EndSysreg
>
> PAS and SH look like they should be enums, Attr is a bit more complex so
> Field is probably a good fit there. Adding the enum information could
> be done incrementally though so:
Will fold the following changes in this patch.
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2246,8 +2246,17 @@ EndSysreg
Sysreg TRBMAR_EL1 3 0 9 11 4
Res0 63:12
-Field 11:10 PAS
-Field 9:8 SH
+Enum 11:10 PAS
+ 0b00 SECURE
+ 0b01 NON_SECURE
+ 0b10 ROOT
+ 0b11 REALM
+EndEnum
+Enum 9:8 SH
+ 0b00 NON_SHAREABLE
+ 0b10 OUTER_SHAREABLE
+ 0b11 INNER_SHAREABLE
+EndEnum
Field 7:0 Attr
EndSysreg
>
> Reviewed-by: Mark Brown <broonie@...nel.org>
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