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Message-ID: <20230613-outskirts-dove-e3e39b096647-mkl@pengutronix.de>
Date:   Tue, 13 Jun 2023 09:52:51 +0200
From:   Marc Kleine-Budde <mkl@...gutronix.de>
To:     Srinivas Goud <srinivas.goud@....com>
Cc:     wg@...ndegger.com, davem@...emloft.net, edumazet@...gle.com,
        kuba@...nel.org, pabeni@...hat.com, gcnu.goud@...il.com,
        git@....com, michal.simek@...inx.com, linux-can@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’

On 12.06.2023 17:12:55, Srinivas Goud wrote:
> ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller.
> Part of this feature configuration and counter registers
> added in IP for 1bit/2bit ECC errors.
> Please find more details in PG096 v5.1 document.
> 
> xlnx,has-ecc is optional property and added to Xilinx CAN
> Controller node if ECC block enabled in the HW.
> 
> Signed-off-by: Srinivas Goud <srinivas.goud@....com>

Is there a way to introspect the IP core to check if this feature is
compiled in?

Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
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