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Message-ID: <919a361dd5f54e738d4824f8096d243c@AcuMS.aculab.com>
Date: Tue, 13 Jun 2023 08:05:27 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Stephen Boyd' <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC: Christopher Obbard <chris.obbard@...labora.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
"kernel@...labora.com" <kernel@...labora.com>
Subject: RE: [PATCH v2 2/2] clk: divider: Fix divisions
From: Stephen Boyd
> Sent: 13 June 2023 01:42
>
> Quoting Sebastian Reichel (2023-05-26 10:10:57)
> > The clock framework handles clock rates as "unsigned long", so u32 on
> > 32-bit architectures and u64 on 64-bit architectures.
> >
> > The current code pointlessly casts the dividend to u64 on 32-bit
> > architectures and thus pointlessly reducing the performance.
>
> It looks like that was done to make the DIV_ROUND_UP() macro not
> overflow the dividend on 32-bit machines (from 9556f9dad8f5):
>
> DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G
> = OVERFLOW / 1.5G
Maybe add:
#define DIV_ROUND_UP_NZ(x, y) (((x) - 1)/(y) + 1)
which doesn't overflow but requires x != 0.
David
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