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Message-ID: <20230613095506.547-1-ravi.bangoria@amd.com>
Date: Tue, 13 Jun 2023 15:25:02 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: <acme@...nel.org>
CC: <ravi.bangoria@....com>, <irogers@...gle.com>, <jolsa@...nel.org>,
<namhyung@...nel.org>, <mark.rutland@....com>,
<peterz@...radead.org>, <adrian.hunter@...el.com>,
<kan.liang@...ux.intel.com>, <james.clark@....com>,
<alisaidi@...zon.com>, <leo.yan@...aro.org>, <maddy@...ux.ibm.com>,
<linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<sandipan.das@....com>, <ananth.narayan@....com>,
<santosh.shukla@....com>
Subject: [PATCH 0/4] perf mem amd: Fix few logic bugs
Recent pmu refactoring changes[1] introduced a notion of core vs other
pmus and made perf mem/c2c code depend only on core pmus, which is
logically wrong for AMD as perf mem/c2c on AMD depends on IBS OP pmu,
not the core pmu. Although user visible perf mem/c2c functionality is
still working fine, internal code logic is wrong. Fix those.
[1] https://lore.kernel.org/r/20230527072210.2900565-1-irogers@google.com
Ravi Bangoria (4):
perf pmus: Describe semantics of 'core_pmus' and 'other_pmus'
perf tool x86: Consolidate is_amd check into single function
perf mem amd: Fix perf_pmus__num_mem_pmus()
perf mem amd: Scan all PMUs instead of just core ones
tools/perf/arch/x86/util/Build | 1 +
tools/perf/arch/x86/util/env.c | 19 +++++++++++++++++++
tools/perf/arch/x86/util/env.h | 7 +++++++
tools/perf/arch/x86/util/evsel.c | 16 ++--------------
tools/perf/arch/x86/util/mem-events.c | 24 +++++++-----------------
tools/perf/arch/x86/util/pmu.c | 15 +++++++++++++++
tools/perf/util/mem-events.c | 16 ++++++++++++----
tools/perf/util/mem-events.h | 1 +
tools/perf/util/pmus.c | 15 ++++++++++++++-
9 files changed, 78 insertions(+), 36 deletions(-)
create mode 100644 tools/perf/arch/x86/util/env.c
create mode 100644 tools/perf/arch/x86/util/env.h
--
2.40.1
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