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Message-ID: <8bfffd83-f4a3-445b-9343-7325c671bd00@sirena.org.uk>
Date:   Tue, 13 Jun 2023 12:02:31 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Anshuman Khandual <anshuman.khandual@....com>
Cc:     linux-arm-kernel@...ts.infradead.org,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh@...nel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        James Morse <james.morse@....com>, kvmarm@...ts.linux.dev,
        coresight@...ts.linaro.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 14/14] arm64/sysreg: Convert TRBIDR_EL1 register to
 automatic generation

On Tue, Jun 13, 2023 at 09:56:31AM +0530, Anshuman Khandual wrote:

>  Sysreg TRBIDR_EL1      3       0       9       11      7
>  Res0   63:12
> -Field  11:8    EA
> +Enum   11:8    EA
> +       0b0000  NON_DESC
> +       0b0001  IGNORE
> +       0b0010  SERROR
> +EndEnum

Sure.

> >> +Field	3:0	Align
> > 
> > Align arguably too though really it's just encoding the relevant power
> > of 2 with the enum coming from the fact that it's limited to at most 2KB
> > alignment so a Field may well make more sense.
> 
> Can fold the following changes in this patch (if required) unless the Field
> looks better than Enum.
> 
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2275,5 +2275,18 @@ EndEnum
>  Res0   7:6
>  Field  5       F
>  Field  4       P
> -Field  3:0     Align
> +Enum   3:0     Align
> +       0b0000  BYTE
> +       0b0001  HALF_WORD
> +       0b0010  WORD

I'm not sure this one makes sense as an enum, though it is technically
one.

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