linux-kernel - Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support

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Date:   Wed, 14 Jun 2023 17:43:57 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Prabhakar <prabhakar.csengg@...il.com>,
        Arnd Bergmann <arnd@...db.de>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Guo Ren <guoren@...nel.org>,
        Andrew Jones <ajones@...tanamicro.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Samuel Holland <samuel@...lland.org>,
        linux-riscv@...ts.infradead.org,
        Christoph Hellwig <hch@...radead.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache
 operations support

On Wed, Jun 14, 2023 at 02:53:26PM +0200, Geert Uytterhoeven wrote:
> Hi Prabhakar,
> 
> On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Introduce support for nonstandard noncoherent systems in the RISC-V
> > architecture. It enables function pointer support to handle cache
> > management in such systems.
> >
> > This patch adds a new configuration option called
> > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
> > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
> > support for cache management in nonstandard noncoherent systems.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v8 -> v9
> > * New patch
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/dma-noncoherent.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 Renesas Electronics Corp.
> > + */
> > +
> > +#ifndef __ASM_DMA_NONCOHERENT_H
> > +#define __ASM_DMA_NONCOHERENT_H
> > +
> > +#include <linux/dma-direct.h>
> > +
> > +/*
> > + * struct riscv_cache_ops - Structure for CMO function pointers
> > + *
> > + * @clean: Function pointer for clean cache
> > + * @inval: Function pointer for invalidate cache
> > + * @flush: Function pointer for flushing the cache
> > + */
> > +struct riscv_cache_ops {
> > +       void (*clean)(phys_addr_t paddr, unsigned long size);
> > +       void (*inval)(phys_addr_t paddr, unsigned long size);
> > +       void (*flush)(phys_addr_t paddr, unsigned long size);
> > +};
> 
> I guess the naming can be improved?
> 
> .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(),
> .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(),
> .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent().
> 
> Perhaps .wback(), .inv(), .wback_inv() are more clear?
> 
> I understand this is subject to bikeshedding...
> But hey, how many innocent bits of data have already been lost due
> to cache semantic mismatches?

Given this is based on Arnd's stuff, +1 on the bikeshed. The names have
been chosen I guess to match the CBOM extensions naming.

Otherwise, I had it in my head that the next revision of this was going
to take patches 8 & 9 from Arnd's series, to align the semantics. Not
that it really bothers me, just means this will have to wait for the
cross-arch series, when pretty sure Arnd suggested not depending on that
any more... Am I missing something Prabhakar?

Other than the bikeshedding, no objections.
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

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