linux-kernel - Re: [PATCH 3/4] perf mem amd: Fix perf_pmus__num_mem

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Date:   Wed, 14 Jun 2023 09:19:59 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Ian Rogers <irogers@...gle.com>
Cc:     acme@...nel.org, jolsa@...nel.org, namhyung@...nel.org,
        mark.rutland@....com, peterz@...radead.org,
        adrian.hunter@...el.com, kan.liang@...ux.intel.com,
        james.clark@....com, alisaidi@...zon.com, leo.yan@...aro.org,
        maddy@...ux.ibm.com, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, sandipan.das@....com,
        ananth.narayan@....com, santosh.shukla@....com,
        Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 3/4] perf mem amd: Fix perf_pmus__num_mem_pmus()

>> +int perf_pmus__num_mem_pmus(void)
>> +{
>> +       /*
>> +        * AMD does not have hybrid cores and also uses IBS OP
>> +        * pmu for perf mem/c2c.
>> +        */
>> +       if (x86__is_amd_cpu())
>> +               return 1;
> 
> The code and comment seem out of sync here. For the hybrid part
> perf_pmus__num_core_pmus() will yield 1 if there is no hybrid, so we
> can just use perf_pmus__num_core_pmus(). For the IBS OP part, does
> that mean that AMD should have 2 mem pmus? Or is IBS OP a core PMU?

Sure. Let me remove hybrid part from the comment.

There are two IBS pmus: ibs_fetch// and ibs_op//. Both of them are
independent of the core pmu (cpu//). An instance of all 3 pmus is
present in each hw SMT thread. And, perf mem/c2c internally uses
ibs_op// pmu on AMD. See tools/perf/arch/x86/util/mem-events.c

  static struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = {
          E(NULL,         NULL,           NULL),
          E(NULL,         NULL,           NULL),
          E("mem-ldst",   "ibs_op//",     "ibs_op"),
  };

Hope this clarifies.

> Can we add this as an example in the core/other documentation in patch
> 1, as you've done for ARM, for clarity.

Sure. Let me also add IBS example in the patch #1 comment.

Thanks,
Ravi