| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <4583d8df9711fad708da3437284734364610d268.camel@mediatek.com>
Date: Wed, 14 Jun 2023 07:44:01 +0000
From: Maso Huang (黃加竹)
<Maso.Huang@...iatek.com>
To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
Trevor Wu (吳文良) <Trevor.Wu@...iatek.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Allen-KH Cheng (程冠勳)
<Allen-KH.Cheng@...iatek.com>,
"renzhijie2@...wei.com" <renzhijie2@...wei.com>,
"tiwai@...e.com" <tiwai@...e.com>,
"Claudiu.Beznea@...rochip.com" <Claudiu.Beznea@...rochip.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"arnd@...db.de" <arnd@...db.de>, "perex@...ex.cz" <perex@...ex.cz>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>,
Jiaxin Yu (俞家鑫) <Jiaxin.Yu@...iatek.com>
Subject: Re: [PATCH 2/7] ASoC: mediatek: mt79xx: support audio clock control
On Tue, 2023-06-13 at 07:27 +0000, Claudiu.Beznea@...rochip.com wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12.06.2023 13:52, Maso Hunag wrote:
> > [You don't often get email from maso.huang@...iatek.com. Learn why
> this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> >
> > From: Maso Huang <maso.huang@...iatek.com>
> >
> > Add audio clock wrapper and audio tuner control.
> >
> > Signed-off-by: Maso Huang <maso.huang@...iatek.com>
> > ---
> > sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c | 123
> +++++++++++++++++++++
> > sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h | 18 +++
> > 2 files changed, 141 insertions(+)
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> >
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > new file mode 100644
> > index 000000000000..f00f0d7de861
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > @@ -0,0 +1,123 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * mt79xx-afe-clk.c -- MediaTek 79xx afe clock ctrl
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <vic.wu@...iatek.com>
> > + * Maso Huang <maso.huang@...iatek.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +
> > +#include "mt79xx-afe-common.h"
> > +#include "mt79xx-afe-clk.h"
> > +#include "mt79xx-reg.h"
> > +
> > +enum {
> > + CK_INFRA_AUD_BUS_CK = 0,
> > + CK_INFRA_AUD_26M_CK,
> > + CK_INFRA_AUD_L_CK,
> > + CK_INFRA_AUD_AUD_CK,
> > + CK_INFRA_AUD_EG2_CK,
> > + CLK_NUM
> > +};
> > +
> > +static const char *aud_clks[CLK_NUM] = {
> > + [CK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
> > + [CK_INFRA_AUD_26M_CK] = "aud_26m_ck",
> > + [CK_INFRA_AUD_L_CK] = "aud_l_ck",
> > + [CK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
> > + [CK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
> > +};
> > +
> > +int mt79xx_init_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > + int i;
> > +
> > + afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM,
> sizeof(*afe_priv->clk),
> > + GFP_KERNEL);
> > + if (!afe_priv->clk)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < CLK_NUM; i++) {
> > + afe_priv->clk[i] = devm_clk_get(afe->dev,
> aud_clks[i]);
> > + if (IS_ERR(afe_priv->clk[i])) {
> > + dev_err(afe->dev, "%s(), devm_clk_get %s
> fail,
> > + ret %ld\n", __func__, aud_clks[i],
> > + PTR_ERR(afe_priv->clk[i]));
> > + return PTR_ERR(afe_priv->clk[i]);
> > + }
> > + }
>
> You can use devm_clk_bulk_get()
>
Hi Claudiu,
Thanks for your review.
I'll use this api in v2 patch.
> > +
> > + return 0;
> > +}
> > +
> > +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_BUS_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_BUS_CK],
> ret);
> > + goto CK_INFRA_AUD_BUS_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_26M_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_26M_CK],
> ret);
> > + goto CK_INFRA_AUD_26M_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_L_CK],
> ret);
> > + goto CK_INFRA_AUD_L_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_AUD_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_AUD_CK],
> ret);
> > + goto CK_INFRA_AUD_AUD_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_EG2_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_EG2_CK],
> ret);
> > + goto CK_INFRA_AUD_EG2_CK_ERR;
> > + }
>
> And clk_bulk_prepare_enable() instead all these.
>
I'll use this api in v2 patch.
> > +
> > + return 0;
> > +
> > +CK_INFRA_AUD_EG2_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> > +CK_INFRA_AUD_AUD_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > +CK_INFRA_AUD_L_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> > +CK_INFRA_AUD_26M_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> > +CK_INFRA_AUD_BUS_CK_ERR:
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(mt79xx_afe_enable_clock);
> > +
> > +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > +
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> > +
>
> And also clk_bulk_disable_unprepare() here.
>
I'll use this api in v2 patch.
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(mt79xx_afe_disable_clock);
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> > new file mode 100644
> > index 000000000000..bf9c3edb6922
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * mt79xx-afe-clk.h -- MediaTek 79xx afe clock ctrl definition
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <vic.wu@...iatek.com>
> > + * Maso Huang <maso.huang@...iatek.com>
> > + */
> > +
> > +#ifndef _MT79XX_AFE_CLK_H_
> > +#define _MT79XX_AFE_CLK_H_
> > +
> > +struct mtk_base_afe;
> > +
> > +int mt79xx_init_clock(struct mtk_base_afe *afe);
> > +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe);
> > +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe);
> > +#endif
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
Best regards,
Maso
Powered by blists - more mailing lists