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Message-Id: <20230614012913.122220-3-yang.lee@linux.alibaba.com>
Date:   Wed, 14 Jun 2023 09:29:13 +0800
From:   Yang Li <yang.lee@...ux.alibaba.com>
To:     sboyd@...nel.org
Cc:     mturquette@...libre.com, orsonzhai@...il.com,
        baolin.wang@...ux.alibaba.com, zhang.lyra@...il.com,
        pdeschrijver@...dia.com, pgaikwad@...dia.com,
        thierry.reding@...il.com, jonathanh@...dia.com,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Yang Li <yang.lee@...ux.alibaba.com>,
        Abaci Robot <abaci@...ux.alibaba.com>
Subject: [PATCH -next 3/3] clk: tegra: Fix unsigned comparison with less than zero

The return value of the round_rate() is long. However, the
return value is being assigned to an unsigned long variable
'rate', so making 'rate' to long.

silence the warnings:
./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0

Reported-by: Abaci Robot <abaci@...ux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@...ux.alibaba.com>
---
 drivers/clk/tegra/clk-periph.c | 2 +-
 drivers/clk/tegra/clk-super.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 0626650a7011..9eaac49facd4 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -51,7 +51,7 @@ static int clk_periph_determine_rate(struct clk_hw *hw,
 	struct tegra_clk_periph *periph = to_clk_periph(hw);
 	const struct clk_ops *div_ops = periph->div_ops;
 	struct clk_hw *div_hw = &periph->divider.hw;
-	unsigned long rate;
+	long rate;
 
 	__clk_hw_set_clk(div_hw, hw);
 
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ec47942720c..7a121de526c0 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -147,7 +147,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
 {
 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
 	struct clk_hw *div_hw = &super->frac_div.hw;
-	unsigned long rate;
+	long rate;
 
 	__clk_hw_set_clk(div_hw, hw);
 
-- 
2.20.1.7.g153144c

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