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Message-ID: <PH8PR12MB667577C4800ED8E82C36D57DE15AA@PH8PR12MB6675.namprd12.prod.outlook.com>
Date: Wed, 14 Jun 2023 10:22:11 +0000
From: "Goud, Srinivas" <srinivas.goud@....com>
To: Marc Kleine-Budde <mkl@...gutronix.de>
CC: "wg@...ndegger.com" <wg@...ndegger.com>,
"davem@...emloft.net" <davem@...emloft.net>,
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"gcnu.goud@...il.com" <gcnu.goud@...il.com>,
"git (AMD-Xilinx)" <git@....com>,
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<linux-arm-kernel@...ts.infradead.org>,
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Subject: RE: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property ‘xlnx,has-ecc’
Hi,
>-----Original Message-----
>From: Marc Kleine-Budde <mkl@...gutronix.de>
>Sent: Tuesday, June 13, 2023 1:23 PM
>To: Goud, Srinivas <srinivas.goud@....com>
>Cc: wg@...ndegger.com; davem@...emloft.net; edumazet@...gle.com;
>kuba@...nel.org; pabeni@...hat.com; gcnu.goud@...il.com; git (AMD-
>Xilinx) <git@....com>; michal.simek@...inx.com; linux-can@...r.kernel.org;
>linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org
>Subject: Re: [PATCH 1/3] dt-bindings: can: xilinx_can: Add ECC property
>‘xlnx,has-ecc’
>
>On 12.06.2023 17:12:55, Srinivas Goud wrote:
>> ECC feature added to Tx and Rx FIFO’s for Xilinx CAN Controller.
>> Part of this feature configuration and counter registers added in IP
>> for 1bit/2bit ECC errors.
>> Please find more details in PG096 v5.1 document.
>>
>> xlnx,has-ecc is optional property and added to Xilinx CAN Controller
>> node if ECC block enabled in the HW.
>>
>> Signed-off-by: Srinivas Goud <srinivas.goud@....com>
>
>Is there a way to introspect the IP core to check if this feature is compiled in?
There is no way(IP registers) to indicate whether ECC feature is enabled or not.
>
>Marc
>
>--
>Pengutronix e.K. | Marc Kleine-Budde |
>Embedded Linux | https://www.pengutronix.de |
>Vertretung Nürnberg | Phone: +49-5121-206917-129 |
>Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
Thanks,
Srinivas
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