linux-kernel - Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

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Date:   Wed, 14 Jun 2023 13:35:23 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Hsiao Chien Sung <shawn.sung@...iatek.com>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Singo Chang <singo.chang@...iatek.com>,
        Nancy Lin <nancy.lin@...iatek.com>,
        Jason-JH Lin <jason-jh.lin@...iatek.com>
Subject: Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
> Add MT8188 VDO1 reset bit map.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@...iatek.com>
> ---
>   drivers/soc/mediatek/mt8188-mmsys.h | 57 +++++++++++++++++++++++++++++
>   drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>   2 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
> index c3e3c5cfe931..208d4dfedc1a 100644
> --- a/drivers/soc/mediatek/mt8188-mmsys.h
> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>   	[MT8188_VDO0_RST_DISP_RSZ0]	= 31,
>   };
> 
> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
> +	[MT8188_VDO1_RST_SMI_LARB2]			= 0,
> +	[MT8188_VDO1_RST_SMI_LARB3]			= 1,
> +	[MT8188_VDO1_RST_GALS]				= 2,
> +	[MT8188_VDO1_RST_FAKE_ENG0]			= 3,
> +	[MT8188_VDO1_RST_FAKE_ENG1]			= 4,
> +	[MT8188_VDO1_RST_MDP_RDMA0]			= 5,
> +	[MT8188_VDO1_RST_MDP_RDMA1]			= 6,
> +	[MT8188_VDO1_RST_MDP_RDMA2]			= 7,
> +	[MT8188_VDO1_RST_MDP_RDMA3]			= 8,
> +	[MT8188_VDO1_RST_VPP_MERGE0]			= 9,
> +	[MT8188_VDO1_RST_VPP_MERGE1]			= 10,
> +	[MT8188_VDO1_RST_VPP_MERGE2]			= 11,
> +	[MT8188_VDO1_RST_VPP_MERGE3]			= 32 + 0,

Works, but there's a better way.

32 + 0 means that you're using reset SW1 register, so you can do

#define MT8188_MMSYS_RST_NR_PER_BANK	32
#define MT8188_RST_SW1_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK
#define MT8188_RST_SW2_OFFSET		MT8188_MMSYS_RST_NR_PER_BANK * 2

[MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
[MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
.......
[MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
...etc

Reading this will make it clear that a certain reset bit is in a different
(sequential or not) register.

P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all reset registers
for all SoCs are always 32 bits, which I believe is true), you could move that
definition to mtk-mmsys.h as
       #define MMSYS_RST_NR_PER_BANK	32
and then define the offsets in mt8188-mmsys.h as
       #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
       .... etc

Thanks,
Angelo