linux-kernel - Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support

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Message-ID: <CAMuHMdWApGKsS8DU7-=6j6WaRBDZ8Amig2NtA8f8=PbGKoFQjQ@mail.gmail.com>
Date:   Wed, 14 Jun 2023 14:53:26 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Prabhakar <prabhakar.csengg@...il.com>
Cc:     Arnd Bergmann <arnd@...db.de>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Guo Ren <guoren@...nel.org>,
        Andrew Jones <ajones@...tanamicro.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Samuel Holland <samuel@...lland.org>,
        linux-riscv@...ts.infradead.org,
        Christoph Hellwig <hch@...radead.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache
 operations support

Hi Prabhakar,

On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Introduce support for nonstandard noncoherent systems in the RISC-V
> architecture. It enables function pointer support to handle cache
> management in such systems.
>
> This patch adds a new configuration option called
> "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
> depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
> support for cache management in nonstandard noncoherent systems.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> v8 -> v9
> * New patch

Thanks for your patch!

> --- /dev/null
> +++ b/arch/riscv/include/asm/dma-noncoherent.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +
> +#ifndef __ASM_DMA_NONCOHERENT_H
> +#define __ASM_DMA_NONCOHERENT_H
> +
> +#include <linux/dma-direct.h>
> +
> +/*
> + * struct riscv_cache_ops - Structure for CMO function pointers
> + *
> + * @clean: Function pointer for clean cache
> + * @inval: Function pointer for invalidate cache
> + * @flush: Function pointer for flushing the cache
> + */
> +struct riscv_cache_ops {
> +       void (*clean)(phys_addr_t paddr, unsigned long size);
> +       void (*inval)(phys_addr_t paddr, unsigned long size);
> +       void (*flush)(phys_addr_t paddr, unsigned long size);
> +};

I guess the naming can be improved?

.clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(),
.inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(),
.flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent().

Perhaps .wback(), .inv(), .wback_inv() are more clear?

I understand this is subject to bikeshedding...
But hey, how many innocent bits of data have already been lost due
to cache semantic mismatches?

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds