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Message-Id: <20230615-viper-stoic-1ff8efd7d51d@spud>
Date:   Thu, 15 Jun 2023 23:50:15 +0100
From:   Conor Dooley <conor@...nel.org>
To:     palmer@...belt.com
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v2 2/2] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

From: Conor Dooley <conor.dooley@...rochip.com>

To permit validation of cpu nodes, swap "additionalProperties: true"
out for "unevaluatedProperties: false".

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e89a10d9c06b..144da86718c1 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -143,7 +143,7 @@ required:
   - riscv,isa
   - interrupt-controller
 
-additionalProperties: true
+unevaluatedProperties: false
 
 examples:
   - |
-- 
2.39.2

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