linux-kernel - Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d8dbb374-b34a-a69a-289d-d051a757bbf3@collabora.com>
Date:   Thu, 15 Jun 2023 09:37:34 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Shawn Sung (宋孝謙) 
        <Shawn.Sung@...iatek.com>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Singo Chang (張興國) 
        <Singo.Chang@...iatek.com>,
        Jason-JH Lin (林睿祥) 
        <Jason-JH.Lin@...iatek.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 12/15] soc: mediatek: Add MT8188 VDO1 reset bit map

Il 15/06/23 08:01, Shawn Sung (宋孝謙) ha scritto:
> Hi Angelo,
> 
> Got it. Will fix this in the next version.
> 
> Added a new define in mtk-mmsys.h:
> #define MMSYS_RST_NR(bank, bit) ((bank * 32) + bit)
> 
> And define the reset table as:
> static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>          [MT8188_VDO1_RST_SMI_LARB2]           = MMSYS_RST_NR(0, 0),
>          ...
>          [MT8188_VDO1_RST_VPP_MERGE2]          = MMSYS_RST_NR(0, 11),
>          [MT8188_VDO1_RST_VPP_MERGE3]          = MMSYS_RST_NR(1, 0),
>          ...
>          [MT8188_VDO1_RST_DISP_RSZ3]           = MMSYS_RST_NR(1, 31),
>          [MT8188_VDO1_RST_HDR_VDO_FE0]         = MMSYS_RST_NR(2, 0),
>      
> ...
>          [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
> };
> 

Okay, that's also good. Go on!

Regards,
Angelo

> Thanks,
> Hsiao Chien Sung
> 
> On Wed, 2023-06-14 at 13:35 +0200, AngeloGioacchino Del Regno wrote:
>>   	
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>   Il 14/06/23 09:31, Hsiao Chien Sung ha scritto:
>>> Add MT8188 VDO1 reset bit map.
>>>
>>> Signed-off-by: Hsiao Chien Sung <shawn.sung@...iatek.com>
>>> ---
>>>    drivers/soc/mediatek/mt8188-mmsys.h | 57
>> +++++++++++++++++++++++++++++
>>>    drivers/soc/mediatek/mtk-mmsys.c    |  3 +-
>>>    2 files changed, 59 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mt8188-mmsys.h
>> b/drivers/soc/mediatek/mt8188-mmsys.h
>>> index c3e3c5cfe931..208d4dfedc1a 100644
>>> --- a/drivers/soc/mediatek/mt8188-mmsys.h
>>> +++ b/drivers/soc/mediatek/mt8188-mmsys.h
>>> @@ -144,6 +144,63 @@ static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
>>>    [MT8188_VDO0_RST_DISP_RSZ0]= 31,
>>>    };
>>>
>>> +static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
>>> +[MT8188_VDO1_RST_SMI_LARB2]= 0,
>>> +[MT8188_VDO1_RST_SMI_LARB3]= 1,
>>> +[MT8188_VDO1_RST_GALS]= 2,
>>> +[MT8188_VDO1_RST_FAKE_ENG0]= 3,
>>> +[MT8188_VDO1_RST_FAKE_ENG1]= 4,
>>> +[MT8188_VDO1_RST_MDP_RDMA0]= 5,
>>> +[MT8188_VDO1_RST_MDP_RDMA1]= 6,
>>> +[MT8188_VDO1_RST_MDP_RDMA2]= 7,
>>> +[MT8188_VDO1_RST_MDP_RDMA3]= 8,
>>> +[MT8188_VDO1_RST_VPP_MERGE0]= 9,
>>> +[MT8188_VDO1_RST_VPP_MERGE1]= 10,
>>> +[MT8188_VDO1_RST_VPP_MERGE2]= 11,
>>> +[MT8188_VDO1_RST_VPP_MERGE3]= 32 + 0,
>>
>> Works, but there's a better way.
>>
>> 32 + 0 means that you're using reset SW1 register, so you can do
>>
>> #define MT8188_MMSYS_RST_NR_PER_BANK32
>> #define MT8188_RST_SW1_OFFSETMT8188_MMSYS_RST_NR_PER_BANK
>> #define MT8188_RST_SW2_OFFSETMT8188_MMSYS_RST_NR_PER_BANK * 2
>>
>> [MT8188_VDO1_RST_VPP_MERGE3] = MT8188_RST_SW1_OFFSET + 0
>> [MT8188_VDO1_RST_VPP_MERGE4] = MT8188_RST_SW1_OFFSET + 0
>> .......
>> [MT8188_VDO1_RST_HDR_VDO_FE0] = MT8188_RST_SW2_OFFSET + 0
>> ...etc
>>
>> Reading this will make it clear that a certain reset bit is in a
>> different
>> (sequential or not) register.
>>
>> P.S.: If the RST_NR_PER_BANK is *not* MT8188 specific (as in, all
>> reset registers
>> for all SoCs are always 32 bits, which I believe is true), you could
>> move that
>> definition to mtk-mmsys.h as
>>         #define MMSYS_RST_NR_PER_BANK32
>> and then define the offsets in mt8188-mmsys.h as
>>         #define MT8188_RST_SW1_OFFSET MMSYS_RST_NR_PER_BANK
>>         .... etc
>>
>> Thanks,
>> Angelo
>>
>>