linux-kernel - Re: [PATCH v2 06/10] drivers: perf: Implement perf event mmap support in the legacy backend

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Message-ID: <4c511218-eb54-0ec4-6820-265f06d91730@ghiti.fr>
Date:   Thu, 15 Jun 2023 09:38:26 +0200
From:   Alexandre Ghiti <alex@...ti.fr>
To:     Andrew Jones <ajones@...tanamicro.com>,
        Alexandre Ghiti <alexghiti@...osinc.com>
Cc:     Jonathan Corbet <corbet@....net>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Ian Rogers <irogers@...gle.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Atish Patra <atishp@...shpatra.org>,
        Anup Patel <anup@...infault.org>,
        Will Deacon <will@...nel.org>, Rob Herring <robh@...nel.org>,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 06/10] drivers: perf: Implement perf event mmap support
 in the legacy backend


On 31/05/2023 16:27, Andrew Jones wrote:
> On Fri, May 12, 2023 at 10:53:17AM +0200, Alexandre Ghiti wrote:
>> Implement the needed callbacks in the legacy driver so that we can
>> directly access the counters through perf in userspace.
>>
>> Signed-off-by: Alexandre Ghiti <alexghiti@...osinc.com>
>> ---
>>   drivers/perf/riscv_pmu_legacy.c | 28 ++++++++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c
>> index ffe09d857366..f0f5bd856f66 100644
>> --- a/drivers/perf/riscv_pmu_legacy.c
>> +++ b/drivers/perf/riscv_pmu_legacy.c
>> @@ -74,6 +74,31 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival)
>>   	local64_set(&hwc->prev_count, initial_val);
>>   }
>>   
>> +static uint8_t pmu_legacy_csr_index(struct perf_event *event)
>> +{
>> +	return event->hw.idx;
>> +}
>> +
>> +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm)
>> +{
>> +	/* In legacy mode, the first 3 CSRs are available. */
> Shouldn't this be
>
>   /* In legacy mode, the first and third CSR are available. */
>
> ?


Yes, I guess this comment is not right in this context, so I'll remove 
the comment entirely as it does bring much.


>> +	if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
>> +	    event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
>> +		return;
>> +
>> +	event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
>> +}
>> +
>> +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm)
>> +{
>> +	/* In legacy mode, the first 3 CSRs are available. */
> same comment
>
>> +	if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&
>> +	    event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)
>> +		return;
>> +
>> +	event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;
>> +}
>> +
>>   /*
>>    * This is just a simple implementation to allow legacy implementations
>>    * compatible with new RISC-V PMU driver framework.
>> @@ -94,6 +119,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu)
>>   	pmu->ctr_get_width = NULL;
>>   	pmu->ctr_clear_idx = NULL;
>>   	pmu->ctr_read = pmu_legacy_read_ctr;
>> +	pmu->event_mapped = pmu_legacy_event_mapped;
>> +	pmu->event_unmapped = pmu_legacy_event_unmapped;
>> +	pmu->csr_index = pmu_legacy_csr_index;
>>   
>>   	perf_pmu_register(&pmu->pmu, RISCV_PMU_LEGACY_PDEV_NAME, PERF_TYPE_RAW);
>>   }
>> -- 
>> 2.37.2
>>
> Otherwise,
>
> Reviewed-by: Andrew Jones <ajones@...tanamicro.com>


Thanks!