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Message-ID: <1ab63d4b-6358-ce08-818a-b5751f88cdde@linaro.org>
Date: Thu, 15 Jun 2023 10:51:30 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Devi Priya <quic_devipriy@...cinc.com>, agross@...nel.org,
andersson@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: quic_srichara@...cinc.com, quic_sjaganat@...cinc.com,
quic_kathirav@...cinc.com, quic_anusha@...cinc.com
Subject: Re: [PATCH] arm64: dts: qcom: ipq9574: Use assigned-clock-rates for
QUP I2C core clks
On 15.06.2023 10:48, Devi Priya wrote:
> Use assigned-clock-rates property for configuring the QUP I2C core clocks
> to operate at nominal frequency.
>
> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
> ---
There's probably some logic behind this, and it almost sounds like
it'd be fitting to introduce an OPP table for I2C hosts, especially
given the voltage requirements.
Konrad
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 0baeb10bbdae..78bf7f9c455a 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -361,6 +361,8 @@
> clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> clock-names = "core", "iface";
> + assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> + assigned-clock-rates = <50000000>;
> dmas = <&blsp_dma 14>, <&blsp_dma 15>;
> dma-names = "tx", "rx";
> status = "disabled";
> @@ -389,6 +391,8 @@
> clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> clock-names = "core", "iface";
> + assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
> + assigned-clock-rates = <50000000>;
> dmas = <&blsp_dma 16>, <&blsp_dma 17>;
> dma-names = "tx", "rx";
> status = "disabled";
> @@ -417,6 +421,8 @@
> clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> clock-names = "core", "iface";
> + assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
> + assigned-clock-rates = <50000000>;
> dmas = <&blsp_dma 18>, <&blsp_dma 19>;
> dma-names = "tx", "rx";
> status = "disabled";
> @@ -446,6 +452,8 @@
> clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> clock-names = "core", "iface";
> + assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
> + assigned-clock-rates = <50000000>;
> dmas = <&blsp_dma 20>, <&blsp_dma 21>;
> dma-names = "tx", "rx";
> status = "disabled";
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