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Message-ID: <20230615090001.10970-1-quic_sridsn@quicinc.com>
Date: Thu, 15 Jun 2023 14:30:01 +0530
From: Sridharan S N <quic_sridsn@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: Sridharan S N <quic_sridsn@...cinc.com>
Subject: [PATCH] arm64: dts: qcom: ipq5332: Add common RDP dtsi file
Add a dtsi file to include interfaces that are common
across IPQ5332 RDPs.
Signed-off-by: Sridharan S N <quic_sridsn@...cinc.com>
---
.../boot/dts/qcom/ipq5332-rdp-common.dtsi | 88 +++++++++++++++++
arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +-------------
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 74 +-------------
arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 58 +----------
arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts | 99 +------------------
5 files changed, 92 insertions(+), 303 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
new file mode 100644
index 000000000000..97dc0e5c15f0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 RDP board common device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "ipq5332.dtsi"
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&blsp1_i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart0 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhc {
+ bus-width = <4>;
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+/* PINCTRL */
+
+&tlmm {
+ i2c_1_pins: i2c-1-state {
+ pins = "gpio29", "gpio30";
+ function = "blsp1_i2c0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio13";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio12";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&xo_board {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
index 3af1d5556950..a376260abefc 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts
@@ -7,83 +7,9 @@
/dts-v1/;
-#include "ipq5332.dtsi"
+#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
-
- aliases {
- serial0 = &blsp1_uart0;
- };
-
- chosen {
- stdout-path = "serial0";
- };
-};
-
-&blsp1_uart0 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_i2c1 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sdhc {
- bus-width = <4>;
- max-frequency = <192000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-0 = <&sdc_default_state>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&xo_board {
- clock-frequency = <24000000>;
-};
-
-/* PINCTRL */
-
-&tlmm {
- i2c_1_pins: i2c-1-state {
- pins = "gpio29", "gpio30";
- function = "blsp1_i2c0";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- sdc_default_state: sdc-default-state {
- clk-pins {
- pins = "gpio13";
- function = "sdc_clk";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio12";
- function = "sdc_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "sdc_data";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
};
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
index bcf3b31c20e3..9ca2c0440b0b 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
@@ -7,32 +7,11 @@
/dts-v1/;
-#include "ipq5332.dtsi"
+#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
-
- aliases {
- serial0 = &blsp1_uart0;
- };
-
- chosen {
- stdout-path = "serial0";
- };
-};
-
-&blsp1_uart0 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_i2c1 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
};
&blsp1_spi0 {
@@ -49,58 +28,7 @@
};
};
-&sdhc {
- bus-width = <4>;
- max-frequency = <192000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-0 = <&sdc_default_state>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&xo_board {
- clock-frequency = <24000000>;
-};
-
-/* PINCTRL */
-
&tlmm {
- i2c_1_pins: i2c-1-state {
- pins = "gpio29", "gpio30";
- function = "blsp1_i2c0";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- sdc_default_state: sdc-default-state {
- clk-pins {
- pins = "gpio13";
- function = "sdc_clk";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio12";
- function = "sdc_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "sdc_data";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
-
spi_0_data_clk_pins: spi-0-data-clk-state {
pins = "gpio14", "gpio15", "gpio16";
function = "blsp0_spi";
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
index 3b6a5cb8bf07..3c8d3225db5a 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -7,25 +7,11 @@
/dts-v1/;
-#include "ipq5332.dtsi"
+#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6";
compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
-
- aliases {
- serial0 = &blsp1_uart0;
- };
-
- chosen {
- stdout-path = "serial0";
- };
-};
-
-&blsp1_uart0 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
};
&blsp1_spi0 {
@@ -42,51 +28,9 @@
};
};
-&sdhc {
- bus-width = <4>;
- max-frequency = <192000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-0 = <&sdc_default_state>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&xo_board {
- clock-frequency = <24000000>;
-};
-
/* PINCTRL */
&tlmm {
- sdc_default_state: sdc-default-state {
- clk-pins {
- pins = "gpio13";
- function = "sdc_clk";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio12";
- function = "sdc_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "sdc_data";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
-
spi_0_data_clk_pins: spi-0-data-clk-state {
pins = "gpio14", "gpio15", "gpio16";
function = "blsp0_spi";
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
index 53c68d8c5e5d..d2b2cb0a8d98 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts
@@ -7,106 +7,9 @@
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "ipq5332.dtsi"
+#include "ipq5332-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9";
compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332";
-
- aliases {
- serial0 = &blsp1_uart0;
- };
-
- chosen {
- stdout-path = "serial0";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&gpio_keys_default_state>;
- pinctrl-names = "default";
-
- button-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- debounce-interval = <60>;
- };
- };
-};
-
-&blsp1_uart0 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_i2c1 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sdhc {
- bus-width = <4>;
- max-frequency = <192000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- pinctrl-0 = <&sdc_default_state>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&xo_board {
- clock-frequency = <24000000>;
-};
-
-/* PINCTRL */
-
-&tlmm {
- gpio_keys_default_state: gpio-keys-default-state {
- pins = "gpio35";
- function = "gpio";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- i2c_1_pins: i2c-1-state {
- pins = "gpio29", "gpio30";
- function = "blsp1_i2c0";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- sdc_default_state: sdc-default-state {
- clk-pins {
- pins = "gpio13";
- function = "sdc_clk";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "gpio12";
- function = "sdc_cmd";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "sdc_data";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
};
--
2.17.1
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