linux-kernel - [PATCH 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

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Message-ID: <20230615111649.36344-2-amit.kumar-mahapatra@amd.com>
Date:   Thu, 15 Jun 2023 16:46:48 +0530
From:   Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>
To:     <tudor.ambarus@...aro.org>, <pratyush@...nel.org>,
        <miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <conor+dt@...nel.org>
CC:     <git@....com>, <michael@...le.cc>, <linux-mtd@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <amitrkcian2002@...il.com>,
        Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>
Subject: [PATCH 1/2] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register

If the WP signal of the flash device is not connected and the software sets
the status register write disable (SRWD) bit in the status register then
thestatus register permanently becomes read-only. To avoid this added a new
boolean DT property "broken-wp". If WP signal is not connected, then this
property should be set in the DT to avoid setting the SRWD during status
register write operation.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@....com>
---
 .../devicetree/bindings/mtd/jedec,spi-nor.yaml      | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 89959e5c47ba..a509d34f14b2 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -70,6 +70,19 @@ properties:
       be used on such systems, to denote the absence of a reliable reset
       mechanism.
 
+  broken-wp:
+    type: boolean
+    description:
+      The SRWD bit in status register, combined with the WP signal provides
+      hardware data protection for the device. When the SRWD bit is set to 1,
+      and the WP signal is driven LOW, the status register nonvolatile bits
+      become read-only and the WRITE STATUS REGISTER operation will not execute.
+      The only way to exit this hardware-protected mode is to drive WP HIGH. But
+      if the WP signal of the flash device is not connected then status register
+      permanently becomes read-only as the SRWD bit cannot be reset. This boolean
+      flag can be used on such systems in which WP signal is not connected, to
+      avoid setting the SRWD bit while writing the status register.
+
   reset-gpios:
     description:
       A GPIO line connected to the RESET (active low) signal of the device.
-- 
2.17.1