linux-kernel - Re: [PATCH 1/3] soc: sifive: Add SiFive private L2 cache support

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Date:   Fri, 16 Jun 2023 21:02:09 +0200
From:   Christophe JAILLET <christophe.jaillet@...adoo.fr>
To:     Eric Lin <eric.lin@...ive.com>, conor@...nel.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        palmer@...belt.com, paul.walmsley@...ive.com,
        aou@...s.berkeley.edu, maz@...nel.org, chenhuacai@...nel.org,
        baolu.lu@...ux.intel.com, will@...nel.org,
        kan.liang@...ux.intel.com, nnac123@...ux.ibm.com,
        pierre.gondois@....com, huangguangbin2@...wei.com, jgross@...e.com,
        chao.gao@...el.com, maobibo@...ngson.cn,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, dslin1010@...il.com
Cc:     Greentime Hu <greentime.hu@...ive.com>,
        Zong Li <zong.li@...ive.com>, Nick Hu <nick.hu@...ive.com>
Subject: Re: [PATCH 1/3] soc: sifive: Add SiFive private L2 cache support

Le 16/06/2023 à 08:32, Eric Lin a écrit :
> This adds SiFive private L2 cache driver which will show
> cache config information when booting and add cpu hotplug
> callback functions.
> 
> Signed-off-by: Eric Lin <eric.lin-SpMDHPYPyPbQT0dZR+AlfA@...lic.gmane.org>
> Signed-off-by: Nick Hu <nick.hu-SpMDHPYPyPbQT0dZR+AlfA@...lic.gmane.org>
> Reviewed-by: Zong Li <zong.li-SpMDHPYPyPbQT0dZR+AlfA@...lic.gmane.org>

[...]

> +static int __init sifive_pl2_cache_init(void)
> +{
> +	int ret;
> +
> +	ret = cpuhp_setup_state(CPUHP_AP_RISCV_SIFIVE_PL2_ONLINE,
> +				"soc/sifive/pl2:online",
> +				      sifive_pl2_online_cpu,
> +				      sifive_pl2_offline_cpu);
> +	if (ret < 0) {
> +		pr_err("Failed to register CPU hotplug notifier %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = platform_driver_register(&sifive_pl2_cache_driver);
> +	if (ret) {
> +		pr_err("Failed to register sifive_pl2_cache_driver: %d\n", ret);

Blind guess: does cpuhp_remove_state() needs to be called?

> +		return ret;
> +	}
> +
> +	sifive_pl2_pm_init();
> +
> +	return ret;

If you send a v2, return 0; would be slighly nicer here.

CJ

> +}

[...]