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Message-Id: <20230616113353.45202-2-xiong.y.zhang@intel.com>
Date: Fri, 16 Jun 2023 19:33:50 +0800
From: Xiong Zhang <xiong.y.zhang@...el.com>
To: kvm@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: seanjc@...gle.com, pbonzini@...hat.com, peterz@...radead.org,
like.xu.linux@...il.com, kan.liang@...ux.intel.com,
zhenyuw@...ux.intel.com, zhiyuan.lv@...el.com,
Xiong Zhang <xiong.y.zhang@...el.com>
Subject: [PATCH 1/4] perf/x86/intel: Get shared reg constraints first for vLBR
When host has per cpu pinned LBR event and guest use LBR also, host
couldn't get correct LBR data, as the physical LBR is preempted by
guest.
The rule for multi events sharing LBR is defined in
__intel_shared_reg_get_constraints(), but guest vLBR event skips this
function, so even if host has per cpu pinned LBR event, guest vLBR event
could get constraints successfully and make vlbr_exclude_host returns true,
finally host couldn't enable LBR in intel_pmu_lbr_enable_all().
This commit move intel_vlbr_constraints() behind
intel_shared_regs_constraints(), guest vLBR event will use LBR also and it
should get LBR resource through intel_shared_regs_constraints().
Fixes: 097e4311cda9 ("perf/x86: Add constraint to create guest LBR event without hw counter")
Signed-off-by: Xiong Zhang <xiong.y.zhang@...el.com>
---
arch/x86/events/intel/core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 6fd3cd97a6ac..2e27a69e9725 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3347,15 +3347,15 @@ __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
{
struct event_constraint *c;
- c = intel_vlbr_constraints(event);
+ c = intel_bts_constraints(event);
if (c)
return c;
- c = intel_bts_constraints(event);
+ c = intel_shared_regs_constraints(cpuc, event);
if (c)
return c;
- c = intel_shared_regs_constraints(cpuc, event);
+ c = intel_vlbr_constraints(event);
if (c)
return c;
--
2.25.1
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