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Date: Fri, 16 Jun 2023 18:19:00 +0530
From: Anusha Canchi <quic_anusha@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
<andersson@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_gokulsri@...cinc.com>,
<quic_sjaganat@...cinc.com>, <quic_kathirav@...cinc.com>,
<quic_arajkuma@...cinc.com>, <quic_poovendh@...cinc.com>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: ipq9574: Add common RDP dtsi file
On 6/14/2023 4:10 PM, Konrad Dybcio wrote:
>
> On 14.06.2023 10:50, Anusha Rao wrote:
>> Add a dtsi file to include interfaces that are common
>> across RDPs.
>>
>> Signed-off-by: Anusha Rao <quic_anusha@...cinc.com>
>> ---
> This enables SDHCI on RDP453. Whether or not it was intended, please
> mention it in the commit message.
Thanks for pointing out! Will address in the next patch.
Thanks,
Anusha
> Konrad
>> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 121 ++++++++++++++++++
>> arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 107 +---------------
>> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 88 +------------
>> arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts | 65 +---------
>> arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 65 +---------
>> 5 files changed, 125 insertions(+), 321 deletions(-)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
>> new file mode 100644
>> index 000000000000..999902bc70bd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
>> @@ -0,0 +1,121 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * IPQ9574 RDP board common device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> + aliases {
>> + serial0 = &blsp1_uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&blsp1_spi0 {
>> + pinctrl-0 = <&spi_0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + flash@0 {
>> + compatible = "micron,n25q128a11", "jedec,spi-nor";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + spi-max-frequency = <50000000>;
>> + };
>> +};
>> +
>> +&blsp1_uart2 {
>> + pinctrl-0 = <&uart2_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&rpm_requests {
>> + regulators {
>> + compatible = "qcom,rpm-mp5496-regulators";
>> +
>> + ipq9574_s1: s1 {
>> + /*
>> + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> + * During regulator registration, kernel not knowing the initial voltage,
>> + * considers it as zero and brings up the regulators with minimum supported voltage.
>> + * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> + * the regulators are brought up with 725mV which is sufficient for all the
>> + * corner parts to operate at 800MHz
>> + */
>> + regulator-min-microvolt = <725000>;
>> + regulator-max-microvolt = <1075000>;
>> + };
>> + };
>> +};
>> +
>> +&sdhc_1 {
>> + pinctrl-0 = <&sdc_default_state>;
>> + pinctrl-names = "default";
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + mmc-hs400-1_8v;
>> + mmc-hs400-enhanced-strobe;
>> + max-frequency = <384000000>;
>> + bus-width = <8>;
>> + status = "okay";
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&tlmm {
>> + sdc_default_state: sdc-default-state {
>> + clk-pins {
>> + pins = "gpio5";
>> + function = "sdc_clk";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + cmd-pins {
>> + pins = "gpio4";
>> + function = "sdc_cmd";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> +
>> + data-pins {
>> + pins = "gpio0", "gpio1", "gpio2",
>> + "gpio3", "gpio6", "gpio7",
>> + "gpio8", "gpio9";
>> + function = "sdc_data";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> +
>> + rclk-pins {
>> + pins = "gpio10";
>> + function = "sdc_rclk";
>> + drive-strength = <8>;
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + spi_0_pins: spi-0-state {
>> + pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> + function = "blsp0_spi";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +};
>> +
>> +&xo_board_clk {
>> + clock-frequency = <24000000>;
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
>> index 2b093e02637b..924e4c50101a 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
>> @@ -8,117 +8,12 @@
>>
>> /dts-v1/;
>>
>> -#include "ipq9574.dtsi"
>> +#include "ipq9574-rdp-common.dtsi"
>>
>> / {
>> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
>> compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
>>
>> - aliases {
>> - serial0 = &blsp1_uart2;
>> - };
>> -
>> - chosen {
>> - stdout-path = "serial0:115200n8";
>> - };
>> -};
>> -
>> -&blsp1_spi0 {
>> - pinctrl-0 = <&spi_0_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -
>> - flash@0 {
>> - compatible = "micron,n25q128a11", "jedec,spi-nor";
>> - reg = <0>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - spi-max-frequency = <50000000>;
>> - };
>> -};
>> -
>> -&blsp1_uart2 {
>> - pinctrl-0 = <&uart2_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> };
>>
>> -&rpm_requests {
>> - regulators {
>> - compatible = "qcom,rpm-mp5496-regulators";
>> -
>> - ipq9574_s1: s1 {
>> - /*
>> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> - * During regulator registration, kernel not knowing the initial voltage,
>> - * considers it as zero and brings up the regulators with minimum supported voltage.
>> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> - * the regulators are brought up with 725mV which is sufficient for all the
>> - * corner parts to operate at 800MHz
>> - */
>> - regulator-min-microvolt = <725000>;
>> - regulator-max-microvolt = <1075000>;
>> - };
>> - };
>> -};
>> -
>> -&sdhc_1 {
>> - pinctrl-0 = <&sdc_default_state>;
>> - pinctrl-names = "default";
>> - mmc-ddr-1_8v;
>> - mmc-hs200-1_8v;
>> - mmc-hs400-1_8v;
>> - mmc-hs400-enhanced-strobe;
>> - max-frequency = <384000000>;
>> - bus-width = <8>;
>> - status = "okay";
>> -};
>>
>> -&sleep_clk {
>> - clock-frequency = <32000>;
>> -};
>> -
>> -&tlmm {
>> - sdc_default_state: sdc-default-state {
>> - clk-pins {
>> - pins = "gpio5";
>> - function = "sdc_clk";
>> - drive-strength = <8>;
>> - bias-disable;
>> - };
>> -
>> - cmd-pins {
>> - pins = "gpio4";
>> - function = "sdc_cmd";
>> - drive-strength = <8>;
>> - bias-pull-up;
>> - };
>> -
>> - data-pins {
>> - pins = "gpio0", "gpio1", "gpio2",
>> - "gpio3", "gpio6", "gpio7",
>> - "gpio8", "gpio9";
>> - function = "sdc_data";
>> - drive-strength = <8>;
>> - bias-pull-up;
>> - };
>> -
>> - rclk-pins {
>> - pins = "gpio10";
>> - function = "sdc_rclk";
>> - drive-strength = <8>;
>> - bias-pull-down;
>> - };
>> - };
>> -
>> - spi_0_pins: spi-0-state {
>> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> - function = "blsp0_spi";
>> - drive-strength = <8>;
>> - bias-disable;
>> - };
>> -};
>> -
>> -&xo_board_clk {
>> - clock-frequency = <24000000>;
>> -};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> index 2b3ed8d351f7..ae2578ba6980 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
>> @@ -8,96 +8,10 @@
>>
>> /dts-v1/;
>>
>> -#include "ipq9574.dtsi"
>> +#include "ipq9574-rdp-common.dtsi"
>>
>> / {
>> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>>
>> - aliases {
>> - serial0 = &blsp1_uart2;
>> - };
>> -
>> - chosen {
>> - stdout-path = "serial0:115200n8";
>> - };
>> -};
>> -
>> -&blsp1_uart2 {
>> - pinctrl-0 = <&uart2_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -};
>> -
>> -&rpm_requests {
>> - regulators {
>> - compatible = "qcom,rpm-mp5496-regulators";
>> -
>> - ipq9574_s1: s1 {
>> - /*
>> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> - * During regulator registration, kernel not knowing the initial voltage,
>> - * considers it as zero and brings up the regulators with minimum supported voltage.
>> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> - * the regulators are brought up with 725mV which is sufficient for all the
>> - * corner parts to operate at 800MHz
>> - */
>> - regulator-min-microvolt = <725000>;
>> - regulator-max-microvolt = <1075000>;
>> - };
>> - };
>> -};
>> -
>> -&sdhc_1 {
>> - pinctrl-0 = <&sdc_default_state>;
>> - pinctrl-names = "default";
>> - mmc-ddr-1_8v;
>> - mmc-hs200-1_8v;
>> - mmc-hs400-1_8v;
>> - mmc-hs400-enhanced-strobe;
>> - max-frequency = <384000000>;
>> - bus-width = <8>;
>> - status = "okay";
>> -};
>> -
>> -&sleep_clk {
>> - clock-frequency = <32000>;
>> -};
>> -
>> -&tlmm {
>> - sdc_default_state: sdc-default-state {
>> - clk-pins {
>> - pins = "gpio5";
>> - function = "sdc_clk";
>> - drive-strength = <8>;
>> - bias-disable;
>> - };
>> -
>> - cmd-pins {
>> - pins = "gpio4";
>> - function = "sdc_cmd";
>> - drive-strength = <8>;
>> - bias-pull-up;
>> - };
>> -
>> - data-pins {
>> - pins = "gpio0", "gpio1", "gpio2",
>> - "gpio3", "gpio6", "gpio7",
>> - "gpio8", "gpio9";
>> - function = "sdc_data";
>> - drive-strength = <8>;
>> - bias-pull-up;
>> - };
>> -
>> - rclk-pins {
>> - pins = "gpio10";
>> - function = "sdc_rclk";
>> - drive-strength = <8>;
>> - bias-pull-down;
>> - };
>> - };
>> -};
>> -
>> -&xo_board_clk {
>> - clock-frequency = <24000000>;
>> };
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
>> index c8fa54e1a62c..d36d1078763e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
>> @@ -8,73 +8,10 @@
>>
>> /dts-v1/;
>>
>> -#include "ipq9574.dtsi"
>> +#include "ipq9574-rdp-common.dtsi"
>>
>> / {
>> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";
>> compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
>>
>> - aliases {
>> - serial0 = &blsp1_uart2;
>> - };
>> -
>> - chosen {
>> - stdout-path = "serial0:115200n8";
>> - };
>> -};
>> -
>> -&blsp1_spi0 {
>> - pinctrl-0 = <&spi_0_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -
>> - flash@0 {
>> - compatible = "micron,n25q128a11", "jedec,spi-nor";
>> - reg = <0>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - spi-max-frequency = <50000000>;
>> - };
>> -};
>> -
>> -&blsp1_uart2 {
>> - pinctrl-0 = <&uart2_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -};
>> -
>> -&rpm_requests {
>> - regulators {
>> - compatible = "qcom,rpm-mp5496-regulators";
>> -
>> - ipq9574_s1: s1 {
>> - /*
>> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> - * During regulator registration, kernel not knowing the initial voltage,
>> - * considers it as zero and brings up the regulators with minimum supported voltage.
>> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> - * the regulators are brought up with 725mV which is sufficient for all the
>> - * corner parts to operate at 800MHz
>> - */
>> - regulator-min-microvolt = <725000>;
>> - regulator-max-microvolt = <1075000>;
>> - };
>> - };
>> -};
>> -
>> -&sleep_clk {
>> - clock-frequency = <32000>;
>> -};
>> -
>> -&tlmm {
>> - spi_0_pins: spi-0-state {
>> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> - function = "blsp0_spi";
>> - drive-strength = <8>;
>> - bias-disable;
>> - };
>> -};
>> -
>> -&xo_board_clk {
>> - clock-frequency = <24000000>;
>> };
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>> index f01de6628c3b..c30c9fbedf26 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
>> @@ -8,73 +8,10 @@
>>
>> /dts-v1/;
>>
>> -#include "ipq9574.dtsi"
>> +#include "ipq9574-rdp-common.dtsi"
>>
>> / {
>> model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
>> compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
>>
>> - aliases {
>> - serial0 = &blsp1_uart2;
>> - };
>> -
>> - chosen {
>> - stdout-path = "serial0:115200n8";
>> - };
>> -};
>> -
>> -&blsp1_spi0 {
>> - pinctrl-0 = <&spi_0_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -
>> - flash@0 {
>> - compatible = "micron,n25q128a11", "jedec,spi-nor";
>> - reg = <0>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - spi-max-frequency = <50000000>;
>> - };
>> -};
>> -
>> -&blsp1_uart2 {
>> - pinctrl-0 = <&uart2_pins>;
>> - pinctrl-names = "default";
>> - status = "okay";
>> -};
>> -
>> -&rpm_requests {
>> - regulators {
>> - compatible = "qcom,rpm-mp5496-regulators";
>> -
>> - ipq9574_s1: s1 {
>> - /*
>> - * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
>> - * During regulator registration, kernel not knowing the initial voltage,
>> - * considers it as zero and brings up the regulators with minimum supported voltage.
>> - * Update the regulator-min-microvolt with SVS voltage of 725mV so that
>> - * the regulators are brought up with 725mV which is sufficient for all the
>> - * corner parts to operate at 800MHz
>> - */
>> - regulator-min-microvolt = <725000>;
>> - regulator-max-microvolt = <1075000>;
>> - };
>> - };
>> -};
>> -
>> -&sleep_clk {
>> - clock-frequency = <32000>;
>> -};
>> -
>> -&tlmm {
>> - spi_0_pins: spi-0-state {
>> - pins = "gpio11", "gpio12", "gpio13", "gpio14";
>> - function = "blsp0_spi";
>> - drive-strength = <8>;
>> - bias-disable;
>> - };
>> -};
>> -
>> -&xo_board_clk {
>> - clock-frequency = <24000000>;
>> };
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