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Message-ID: <90f802db-79cc-010a-9a83-c7bdbf0d0c00@linaro.org>
Date: Sat, 17 Jun 2023 10:36:18 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Stanley Chang <stanley_chang@...ltek.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Alan Stern <stern@...land.harvard.edu>,
Flavio Suligoi <f.suligoi@...m.it>,
Bagas Sanjaya <bagasdotme@...il.com>,
Matthias Kaehlcke <mka@...omium.org>,
Ray Chi <raychi@...gle.com>, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-usb@...r.kernel.org
Subject: Re: [PATCH v4 5/5] dt-bindings: phy: realtek: Add the doc about the
Realtek SoC USB 3.0 PHY
On 14/06/2023 11:28, Stanley Chang wrote:
> Add the documentation explain the property about Realtek USB PHY driver.
>
> Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
> controller. Added the driver to drive the USB 3.0 PHY transceivers.
>
> Signed-off-by: Stanley Chang <stanley_chang@...ltek.com>
> ---
> v3 to v4 change:
> 1. Remove the parameter and non hardware properties from dts.
> 2. Using the compatible data included the config and parameter
> in driver.
> v2 to v3 change:
> 1. Broken down into two patches, one for each of USB 2 & 3.
> 2. Add more description about Realtek RTD SoCs architecture.
> 3. Removed parameter v1 support for simplification.
> 4. Revised the compatible name for fallback compatible.
> 5. Remove some properties that can be set in the driver.
> v1 to v2 change:
> Add phy-cells for generic phy driver
> ---
> .../bindings/phy/realtek,usb3phy.yaml | 105 ++++++++++++++++++
> 1 file changed, 105 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml
> new file mode 100644
> index 000000000000..0f849cf942e8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2023 Realtek Semiconductor Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC SoCs USB 3.0 PHY
> +
> +maintainers:
> + - Stanley Chang <stanley_chang@...ltek.com>
> +
> +description:
> + Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
> + The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
> + support multiple XHCI controllers. One PHY device node maps to one XHCI
> + controller.
> +
> + RTD1295/RTD1619 SoCs USB
> + The USB architecture includes three XHCI controllers.
> + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
> + controllers.
> + XHCI controller#0 -- usb2phy -- phy#0
> + |- usb3phy -- phy#0
> + XHCI controller#1 -- usb2phy -- phy#0
> + XHCI controller#2 -- usb2phy -- phy#0
> + |- usb3phy -- phy#0
> +
> + RTD1319/RTD1619b SoCs USB
> + The USB architecture includes three XHCI controllers.
> + Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
> + XHCI controller#0 -- usb2phy -- phy#0
> + XHCI controller#1 -- usb2phy -- phy#0
> + XHCI controller#2 -- usb2phy -- phy#0
> + |- usb3phy -- phy#0
> +
> + RTD1319d SoCs USB
> + The USB architecture includes three XHCI controllers.
> + Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
> + XHCI controller#0 -- usb2phy -- phy#0
> + |- usb3phy -- phy#0
> + XHCI controller#1 -- usb2phy -- phy#0
> + XHCI controller#2 -- usb2phy -- phy#0
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - realtek,rtd1295-usb3phy
> + - realtek,rtd1319-usb3phy
> + - realtek,rtd1319d-usb3phy
> + - realtek,rtd1619-usb3phy
> + - realtek,rtd1619b-usb3phy
> + - const: realtek,usb3phy
Drop last compatible, it is not used now. Does not make sense.
> +
> + reg:
> + description: PHY data registers
Drop description, it's obvious.
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + nvmem-cells:
> + maxItems: 1
> + description: A phandle to the tx lfps swing trim data provided by
> + a nvmem device, if unspecified, default values shall be used.
> +
> + nvmem-cell-names:
> + items:
> + - const: usb_u3_tx_lfps_swing_trim
> +
> + realtek,amplitude-control-coarse-tuning:
> + description:
> + This adjusts the signal amplitude for normal operation and beacon LFPS.
> + This value is a parameter for coarse tuning.
> + For different boards, if the default value is inappropriate, this
> + property can be assigned to adjust.
default:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 255
> +
> + realtek,amplitude-control-fine-tuning:
> + description:
> + This adjusts the signal amplitude for normal operation and beacon LFPS.
> + This value is used for fine-tuning parameters.
> + $ref: /schemas/types.yaml#/definitions/uint32
default:
> + minimum: 0
> + maximum: 65535
> +
Best regards,
Krzysztof
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