[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20230617161529.2092-8-jszhang@kernel.org>
Date: Sun, 18 Jun 2023 00:15:28 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC
Currently, I would like to maintain the T-HEAD RISC-V SoC support.
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e0ad886d3163..68805b09654f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18162,6 +18162,14 @@ F: drivers/perf/riscv_pmu.c
F: drivers/perf/riscv_pmu_legacy.c
F: drivers/perf/riscv_pmu_sbi.c
+RISC-V THEAD SoC SUPPORT
+M: Jisheng Zhang <jszhang@...nel.org>
+M: Guo Ren <guoren@...nel.org>
+M: Fu Wei <wefu@...hat.com>
+L: linux-riscv@...ts.infradead.org
+S: Maintained
+F: arch/riscv/boot/dts/thead/
+
RNBD BLOCK DRIVERS
M: Md. Haris Iqbal <haris.iqbal@...os.com>
M: Jack Wang <jinpu.wang@...os.com>
--
2.40.0
Powered by blists - more mailing lists