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Message-ID: <TYAP286MB0315C35BA080B686EB5EA980BC59A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM>
Date: Sat, 17 Jun 2023 12:51:13 +0800
From: yangshiji66@...look.com
To: sergio.paracuellos@...il.com
Cc: arinc.unal@...nc9.com, devicetree@...r.kernel.org,
john@...ozen.org, krzysztof.kozlowski+dt@...aro.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mips@...r.kernel.org, matthias.bgg@...il.com,
mturquette@...libre.com, p.zabel@...gutronix.de,
robh+dt@...nel.org, sboyd@...nel.org, tsbogend@...ha.franken.de
Subject: Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
Thank you for taking care of these old amazing SoCs. When I ported these
patches to OpenWrt, I found some issues.
>+
>+static const struct of_device_id mtmips_of_match[] = {
>+ {
>+ .compatible = "ralink,rt2880-sysc",
>+ .data = &rt2880_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,rt3050-sysc",
>+ .data = &rt3050_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,rt3052-sysc",
>+ .data = &rt3052_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,rt3352-sysc",
>+ .data = &rt3052_clk_data,
It seems that there should be `.data = &rt3352_clk_data,`?
>+ },
>+ {
>+ .compatible = "ralink,rt3883-sysc",
>+ .data = &rt3352_clk_data,
>+ },
And there should be `.data = &rt3883_clk_data,`?
>+ {
>+ .compatible = "ralink,rt5350-sysc",
>+ .data = &rt5350_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,mt7620a-sysc",
>+ .data = &mt7620_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,mt7620-sysc",
>+ .data = &mt7620_clk_data,
>+ },
>+ {
I am confused about the difference between `ralink,mt7620-sysc` and
`ralink,mt7620a-sysc`. Do you mean mt7620n?
https://www.mediatek.com/products/home-networking/mt7620n-a
>+ .compatible = "ralink,mt7628-sysc",
>+ .data = &mt76x8_clk_data,
>+ },
>+ {
>+ .compatible = "ralink,mt7688-sysc",
>+ .data = &mt76x8_clk_data,
>+ },
>+ {}
>+};
>+
Thanks,
Shiji Yang
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