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Message-ID: <8d5f38e6-2ca6-2c61-da29-1d4d2a3df569@linaro.org>
Date: Sun, 18 Jun 2023 20:49:52 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: niravkumar.l.rabara@...el.com, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Andrew Lunn <andrew@...n.ch>,
Dinh Nguyen <dinguyen@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Wen Ping <wen.ping.teh@...el.com>,
Richard Cochran <richardcochran@...il.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, netdev@...r.kernel.org,
Adrian Ng Ho Yin <adrian.ho.yin.ng@...el.com>
Subject: Re: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and
resets
On 18/06/2023 15:22, niravkumar.l.rabara@...el.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
>
> Add clock and reset ID definitions for Intel Agilex5 SoCFPGA
>
> Co-developed-by: Teh Wen Ping <wen.ping.teh@...el.com>
> Signed-off-by: Teh Wen Ping <wen.ping.teh@...el.com>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> ---
> .../bindings/clock/intel,agilex5.yaml | 42 ++++++++
> include/dt-bindings/clock/agilex5-clock.h | 100 ++++++++++++++++++
> .../dt-bindings/reset/altr,rst-mgr-agilex5.h | 79 ++++++++++++++
> 3 files changed, 221 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml
> create mode 100644 include/dt-bindings/clock/agilex5-clock.h
> create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h
>
> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml
> new file mode 100644
> index 000000000000..e408c52deefa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml
Filename matching compatible, so missing "clk"
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/intel,agilex5.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel SoCFPGA Agilex5 platform clock controller binding
Drop "binding"
> +
> +maintainers:
> + - Teh Wen Ping <wen.ping.teh@...el.com>
> + - Niravkumar L Rabara <niravkumar.l.rabara@...el.com>
> +
> +description:
> + The Intel Agilex5 Clock controller is an integrated clock controller, which
> + generates and supplies to all modules.
"generates and supplies" what?
> +
> +properties:
> + compatible:
> + const: intel,agilex5-clkmgr
Why "clkmgr", not "clk"? You did not call it Clock manager anywhere in
the description or title.
> +
> + '#clock-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
Keep the same order as in properties:
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node:
> + - |
> + clkmgr: clock-controller@...10000 {
> + compatible = "intel,agilex5-clkmgr";
> + reg = <0x10d10000 0x1000>;
> + #clock-cells = <1>;
> + };
> +...
> diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h
> new file mode 100644
> index 000000000000..4505b352cd83
> --- /dev/null
> +++ b/include/dt-bindings/clock/agilex5-clock.h
Filename the same as binding. Missing vendor prefix, entirely different
device name.
> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (C) 2022, Intel Corporation
> + */
...
> +
> +#endif /* __AGILEX5_CLOCK_H */
> diff --git a/include/dt-bindings/reset/altr,rst-mgr-agilex5.h b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h
> new file mode 100644
> index 000000000000..81e5e8c89893
> --- /dev/null
> +++ b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h
Same filename as binding.
But why do you need this file? Your device is not a reset controller.
Best regards,
Krzysztof
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