linux-kernel - [PATCH v7 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110

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Message-ID: <20230619094759.21013-6-minda.chen@starfivetech.com>
Date:   Mon, 19 Jun 2023 17:47:59 +0800
From:   Minda Chen <minda.chen@...rfivetech.com>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        Conor Dooley <conor@...nel.org>, Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Roger Quadros <rogerq@...nel.org>
CC:     <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-riscv@...ts.infradead.org>,
        "Paul Walmsley" <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Minda Chen <minda.chen@...rfivetech.com>,
        Mason Huo <mason.huo@...rfivetech.com>
Subject: [PATCH v7 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110

Add PCIe PHY dts configuration for StarFive JH7110 SoC.
PCIe0 PHY can be use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7e5c3ae83aa1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,18 @@
 			status = "disabled";
 		};
 
+		pciephy0: phy@...10000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@...20000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		uart3: serial@...00000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
-- 
2.17.1