| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <5b9535d6-d59e-5b8b-2649-3efdb777a8a2@linaro.org>
Date: Mon, 19 Jun 2023 12:09:39 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Georgi Djakov <djakov@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm
nodes
On 19/06/2023 11:55, Konrad Dybcio wrote:
> On 19.06.2023 10:24, Neil Armstrong wrote:
>> Set the proper enable_mask to needs requiring such value
>> to be used instead of a bandwidth when voting.
>>
>> The masks were copied from the downstream implementation at [1].
>>
>> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r1-rel/drivers/interconnect/qcom/kalama.c
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
> The values match downstream, so:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
>
> Since you're already touching this code, may I turn your interest to:
>
> 1. Adding enable_mask-s to 8450 and 8775
>
> 2. Porting https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/d5edeca085f4
>
> 3. Adding the default perf settings for 8450 and 8550
Yep this would be the next steps.
Neil
>
> Konrad
>
>> drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
>> index d823ba988ef6..0864ed285375 100644
>> --- a/drivers/interconnect/qcom/sm8550.c
>> +++ b/drivers/interconnect/qcom/sm8550.c
>> @@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_acv = {
>> .name = "ACV",
>> + .enable_mask = 0x8,
>> .num_nodes = 1,
>> .nodes = { &ebi },
>> };
>> @@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
>>
>> static struct qcom_icc_bcm bcm_cn0 = {
>> .name = "CN0",
>> + .enable_mask = 0x1,
>> .keepalive = true,
>> .num_nodes = 54,
>> .nodes = { &qsm_cfg, &qhs_ahb2phy0,
>> @@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
>>
>> static struct qcom_icc_bcm bcm_co0 = {
>> .name = "CO0",
>> + .enable_mask = 0x1,
>> .num_nodes = 2,
>> .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
>> };
>> @@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
>>
>> static struct qcom_icc_bcm bcm_mm1 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 8,
>> .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
>> &qnm_camnoc_sf, &qnm_vapss_hcp,
>> @@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
>>
>> static struct qcom_icc_bcm bcm_sh1 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 13,
>> .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
>> &chm_apps, &qnm_gpu,
>> @@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
>>
>> static struct qcom_icc_bcm bcm_sn1 = {
>> .name = "SN1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qhm_gic, &xm_gic,
>> &qns_gemnoc_gc },
>> @@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
>>
>> static struct qcom_icc_bcm bcm_acv_disp = {
>> .name = "ACV",
>> + .enable_mask = 0x1,
>> .num_nodes = 1,
>> .nodes = { &ebi_disp },
>> };
>> @@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
>>
>> static struct qcom_icc_bcm bcm_sh1_disp = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 2,
>> .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
>> };
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_0 },
>> };
>> @@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
>> &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
>> @@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
>> &qnm_pcie_cam_ife_0 },
>> @@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_1 },
>> };
>> @@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
>> &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
>> @@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
>> &qnm_pcie_cam_ife_1 },
>> @@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_2 },
>> };
>> @@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
>> &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
>> @@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
>> &qnm_pcie_cam_ife_2 },
>>
Powered by blists - more mailing lists