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Message-ID: <5782c8c2bb3e76a802e4a81c553a21edbaee7c47.camel@intel.com>
Date: Mon, 19 Jun 2023 11:43:45 +0000
From: "Huang, Kai" <kai.huang@...el.com>
To: "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
"Hansen, Dave" <dave.hansen@...el.com>
CC: "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
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"Williams, Dan J" <dan.j.williams@...el.com>
Subject: Re: [PATCH v11 18/20] x86: Handle TDX erratum to reset TDX private
memory during kexec() and reboot
On Mon, 2023-06-12 at 06:47 -0700, Dave Hansen wrote:
> On 6/12/23 03:27, Huang, Kai wrote:
> > So I think a __mb() after setting tdmr->pamt_4k_base should be good enough, as
> > it guarantees when setting to any pamt_*_size happens, the valid pamt_4k_base
> > will be seen by other cpus.
> >
> > Does it make sense?
>
> Just use a normal old atomic_t or set_bit()/test_bit(). They have
> built-in memory barriers are are less likely to get botched.
Hi Dave,
Using atomic_set() requires changing tdmr->pamt_4k_base to atomic_t, which is a
little bit silly or overkill IMHO. Looking at the code, it seems
arch_atomic_set() simply uses __WRITE_ONCE():
static __always_inline void arch_atomic_set(atomic_t *v, int i)
{
__WRITE_ONCE(v->counter, i);
}
Is it better to just use __WRITE_ONCE() or WRITE_ONCE() here?
- tdmr->pamt_4k_base = pamt_base[TDX_PS_4K];
+ WRITE_ONCE(tdmr->pamt_4k_base, pamt_base[TDX_PS_4K]);
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