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Message-ID: <20230620172753.GA3858158-robh@kernel.org>
Date: Tue, 20 Jun 2023 11:27:53 -0600
From: Rob Herring <robh@...nel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Andy Gross <agross@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/3] dt-bindings: pinctrl: qcom,sm8350-lpass-lpi: add
SM8350 LPASS TLMM
On Mon, Jun 19, 2023 at 11:27:33AM +0200, Krzysztof Kozlowski wrote:
> Add bidings for pin controller in SM8350 Low Power Audio SubSystem
bidings?
> (LPASS).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> ---
>
> Changes in v2:
> 1. None
> ---
> .../qcom,sm8350-lpass-lpi-pinctrl.yaml | 144 ++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
> new file mode 100644
> index 000000000000..0fb2002772b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8350 SoC LPASS LPI TLMM
> +
> +maintainers:
> + - Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> + - Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
> +
> +description:
> + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
> + (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
> +
> +properties:
> + compatible:
> + const: qcom,sm8350-lpass-lpi-pinctrl
> +
> + reg:
> + items:
> + - description: LPASS LPI TLMM Control and Status registers
> + - description: LPASS LPI MCC registers
> +
> + clocks:
> + items:
> + - description: LPASS Core voting clock
> + - description: LPASS Audio voting clock
> +
> + clock-names:
> + items:
> + - const: core
> + - const: audio
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + description: Specifying the pin number and flags, as defined in
> + include/dt-bindings/gpio/gpio.h
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> +patternProperties:
> + "-state$":
> + oneOf:
> + - $ref: "#/$defs/qcom-sm8350-lpass-state"
> + - patternProperties:
> + "-pins$":
> + $ref: "#/$defs/qcom-sm8350-lpass-state"
> + additionalProperties: false
> +
> +$defs:
> + qcom-sm8350-lpass-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: /schemas/pinctrl/pincfg-node.yaml
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
> +
> + function:
> + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
> + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
> + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
> + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
> + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
> + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
> + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
> + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> + default: 2
> + description:
> + Selects the drive strength for the specified pins, in mA.
> +
> + slew-rate:
> + enum: [0, 1, 2, 3]
> + default: 0
> + description: |
> + 0: No adjustments
> + 1: Higher Slew rate (faster edges)
> + 2: Lower Slew rate (slower edges)
> + 3: Reserved (No adjustments)
> +
> + bias-bus-hold: true
> + bias-pull-down: true
> + bias-pull-up: true
> + bias-disable: true
> + input-enable: true
> + output-high: true
> + output-low: true
> +
> + required:
> + - pins
> + - function
> +
> + additionalProperties: false
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - gpio-controller
> + - "#gpio-cells"
> + - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/sound/qcom,q6afe.h>
> +
> + lpass_tlmm: pinctrl@...0000 {
Drop unused label.
With those,
Reviewed-by: Rob Herring <robh@...nel.org>
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