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Message-ID: <itxb3tdwvyxzwlzvvbwv75jssjwfpve2k4b4bcfzyp5x5rb6wu@tzlzdn6dem46>
Date: Tue, 20 Jun 2023 11:02:26 -0700
From: Lucas De Marchi <lucas.demarchi@...el.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
CC: Jani Nikula <jani.nikula@...ux.intel.com>,
Andrew Morton <akpm@...ux-foundation.org>,
<intel-gfx@...ts.freedesktop.org>,
Kevin Brodsky <kevin.brodsky@....com>,
<linux-kernel@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
Christian König <christian.koenig@....com>,
Alex Deucher <alexander.deucher@....com>,
"Thomas Gleixner" <tglx@...utronix.de>,
Masahiro Yamada <masahiroy@...nel.org>,
<intel-xe@...ts.freedesktop.org>
Subject: Re: [Intel-xe] [PATCH 2/3] linux/bits.h: Add fixed-width GENMASK and
BIT macros
On Tue, Jun 20, 2023 at 08:41:10PM +0300, Andy Shevchenko wrote:
>On Tue, Jun 20, 2023 at 10:25:21AM -0700, Lucas De Marchi wrote:
>> On Tue, Jun 20, 2023 at 05:55:19PM +0300, Andy Shevchenko wrote:
>> > On Tue, Jun 20, 2023 at 05:47:34PM +0300, Jani Nikula wrote:
>> > > On Thu, 15 Jun 2023, Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote:
>> > > > On Fri, May 12, 2023 at 02:45:19PM +0300, Jani Nikula wrote:
>> > > >> On Fri, 12 May 2023, Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote:
>> > > >> > On Fri, May 12, 2023 at 02:25:18PM +0300, Jani Nikula wrote:
>> > > >> >> On Fri, 12 May 2023, Andy Shevchenko <andriy.shevchenko@...ux.intel.com> wrote:
>> > > >> >> > On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
>> > > >> >> >> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
>> > > >> >> >> masks for fixed-width types and also the corresponding BIT_U32(),
>> > > >> >> >> BIT_U16() and BIT_U8().
>
>> > > >> >> > Why?
>> > > >> >>
>> > > >> >> The main reason is that GENMASK() and BIT() size varies for 32/64 bit
>> > > >> >> builds.
>> > > >> >
>> > > >> > When needed GENMASK_ULL() can be used (with respective castings perhaps)
>> > > >> > and BIT_ULL(), no?
>> > > >>
>> > > >> How does that help with making them the same 32-bit size on both 32 and
>> > > >> 64 bit builds?
>> > > >
>> > > > u32 x = GENMASK();
>> > > > u64 y = GENMASK_ULL();
>> > > >
>> > > > No? Then use in your code either x or y. Note that I assume that the parameters
>> > > > to GENMASK*() are built-time constants. Is it the case for you?
>> > >
>> > > What's wrong with wanting to define macros with specific size, depending
>> > > on e.g. hardware registers instead of build size?
>> >
>> > Nothing, but I think the problem is smaller than it's presented.
>>
>> not sure about big/small problem you are talking about. It's a problem
>> for when the *device* register is a 32b fixed width, which is
>> independent from the CPU you are running on. We also have registers that
>> are u16 and u64. Having fixed-width GENMASK and BIT helps avoiding
>> mistakes like below. Just to use one example, the diff below builds
>> fine on my 64b machine, yet it's obviously wrong:
>>
>> $ git diff diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> index 0b414eae1683..692a0ad9a768 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>> @@ -261,8 +261,8 @@ static u32 rw_with_mcr_steering_fw(struct intel_gt *gt,
>> * No need to save old steering reg value.
>> */
>> intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR,
>> - REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
>> - REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance) |
>> + FIELD_PREP(MTL_MCR_GROUPID, group) |
>> + FIELD_PREP(MTL_MCR_INSTANCEID, instance) |
>> (rw_flag == FW_REG_READ ? GEN11_MCR_MULTICAST : 0));
>> } else if (GRAPHICS_VER(uncore->i915) >= 11) {
>> mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 718cb2c80f79..c42bc2900c6a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -80,8 +80,8 @@
>> #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
>> #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
>> #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
>> -#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
>> -#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
>> +#define MTL_MCR_GROUPID GENMASK(32, 8)
>> +#define MTL_MCR_INSTANCEID GENMASK(3, 0)
>> #define IPEIR_I965 _MMIO(0x2064)
>> #define IPEHR_I965 _MMIO(0x2068)
>>
>> If the driver didn't support 32b CPUs, this would even go unnoticed.
>
>So, what does prevent you from using GENMASK_ULL()?
nothing is preventing me to write the wrong code, which is what we are
trying to solve. GENMASK_ULL() would generate the wrong code as that
particular register is 32b, not 64b, on the GPU.
>
>Another point, you may teach GENMASK() to issue a warning if hi and/or lo
>bigger than BITS_PER_LONG.
Which varies depending on the CPU you are building for, so it misses the
point. GENMASK_U32/GENMASK_U16/GENMASK_U8 and BIT counterparts would
emit a warning if hi is bigger than _exactly_ 32, 16 or 8, regardless
of the CPU you built the code for.
Lucas De Marchi
>
>I still don't see the usefulness of that churn.
>
>> Lucas De Marchi
>>
>> > And there are already header for bitfields with a lot of helpers
>> > for (similar) cases if not yours.
>> >
>> > > What would you use for printk format if you wanted to to print
>> > > GENMASK()?
>> >
>> > %lu, no?
>
>--
>With Best Regards,
>Andy Shevchenko
>
>
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