linux-kernel - Re: [PATCH net-next 3/3] net: dsa: microchip: fix writes to phy registers >= 0x10

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Message-ID: <88474092-70cb-40fc-9c01-1fc8527d5bcb@lunn.ch>
Date:   Tue, 20 Jun 2023 21:28:21 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Rasmus Villemoes <linux@...musvillemoes.dk>
Cc:     Woojung Huh <woojung.huh@...rochip.com>,
        UNGLinuxDriver@...rochip.com,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 3/3] net: dsa: microchip: fix writes to phy
 registers >= 0x10

On Tue, Jun 20, 2023 at 01:38:54PM +0200, Rasmus Villemoes wrote:
> According to the errata sheets for ksz9477 and ksz9567, writes to the
> PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to
> 0xN13f) must be done as a 32 bit write to the 4-byte aligned address
> containing the register, hence requires a RMW in order not to change
> the adjacent PHY register.

ASIC engineers do see to come up with novel ways to break things.

I assume you have not seen real problems with this, which is why it is
not for net and a Fixes: tag?

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew