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Message-ID: <a6d482b5-05d8-01a9-be63-f52ae03e0be5@intel.com>
Date: Tue, 20 Jun 2023 08:15:31 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: David Hildenbrand <david@...hat.com>,
Kai Huang <kai.huang@...el.com>, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Cc: linux-mm@...ck.org, kirill.shutemov@...ux.intel.com,
tony.luck@...el.com, peterz@...radead.org, tglx@...utronix.de,
seanjc@...gle.com, pbonzini@...hat.com, dan.j.williams@...el.com,
rafael.j.wysocki@...el.com, ying.huang@...el.com,
reinette.chatre@...el.com, len.brown@...el.com, ak@...ux.intel.com,
isaku.yamahata@...el.com, chao.gao@...el.com,
sathyanarayanan.kuppuswamy@...ux.intel.com, bagasdotme@...il.com,
sagis@...gle.com, imammedo@...hat.com
Subject: Re: [PATCH v11 05/20] x86/virt/tdx: Add SEAMCALL infrastructure
On 6/19/23 05:52, David Hildenbrand wrote:
>> + /*
>> + * SEAMCALL caused #GP or #UD. By reaching here %eax contains
>> + * the trap number. Convert the trap number to the TDX error
>> + * code by setting TDX_SW_ERROR to the high 32-bits of %rax.
>> + *
>> + * Note cannot OR TDX_SW_ERROR directly to %rax as OR instruction
>> + * only accepts 32-bit immediate at most.
>
> Not sure if that comment is really helpful here. It's a common pattern
> for large immediates, no?
It's a question of whether you write the comments for folks that read
x86 assembly all the time or not.
I think the comment is helpful.
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