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Message-ID: <mhng-5074ab93-a879-4b1c-8f39-0f59b7e0f4f4@palmer-ri-x1c9a>
Date: Wed, 21 Jun 2023 16:37:09 -0700 (PDT)
From: Palmer Dabbelt <palmer@...belt.com>
To: alexghiti@...osinc.com
CC: corbet@....net, peterz@...radead.org, mingo@...hat.com,
acme@...nel.org, Mark Rutland <mark.rutland@....com>,
alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
namhyung@...nel.org, irogers@...gle.com,
Paul Walmsley <paul.walmsley@...ive.com>,
aou@...s.berkeley.edu, atishp@...shpatra.org, anup@...infault.org,
Will Deacon <will@...nel.org>, robh@...nel.org,
ajones@...tanamicro.com, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, alexghiti@...osinc.com
Subject: Re: [PATCH v2 00/10] riscv: Allow userspace to directly access perf counters
On Fri, 12 May 2023 01:53:11 PDT (-0700), alexghiti@...osinc.com wrote:
> riscv used to allow direct access to cycle/time/instret counters,
> bypassing the perf framework, this patchset intends to allow the user to
> mmap any counter when accessed through perf. But we can't break the
> existing behaviour so we introduce a sysctl perf_user_access like arm64
> does, which defaults to the legacy mode described above.
>
> *Note* that there are still ongoing discussions around which mode should
> be the default mode with distro people.
>
> base-commit-tag: v6.3
>
> Changes in v2:
> - Split into smaller patches, way better!
> - Add RB from Conor
> - Simplify the way we checked riscv architecture
> - Fix race mmap and other thread running on other cpus
> - Use hwc when available
> - Set all userspace access flags in event_init, too cumbersome to handle sysctl changes
> - Fix arch_perf_update_userpage for pmu other than riscv-pmu by renaming pmu driver
> - Fixed kernel test robot build error
> - Fixed documentation (Andrew and Bagas)
> - perf testsuite passes mmap tests in all 3 modes
>
> Alexandre Ghiti (10):
> perf: Fix wrong comment about default event_idx
> include: riscv: Fix wrong include guard in riscv_pmu.h
> riscv: Make legacy counter enum match the HW numbering
> drivers: perf: Rename riscv pmu driver
> riscv: Prepare for user-space perf event mmap support
> drivers: perf: Implement perf event mmap support in the legacy backend
> drivers: perf: Implement perf event mmap support in the SBI backend
> Documentation: admin-guide: Add riscv sysctl_perf_user_access
> tools: lib: perf: Implement riscv mmap support
> perf: tests: Adapt mmap-basic.c for riscv
>
> Documentation/admin-guide/sysctl/kernel.rst | 24 ++-
> arch/riscv/kernel/Makefile | 2 +-
> arch/riscv/kernel/perf_event.c | 74 ++++++++
> drivers/perf/riscv_pmu.c | 41 ++++
> drivers/perf/riscv_pmu_legacy.c | 37 +++-
> drivers/perf/riscv_pmu_sbi.c | 196 +++++++++++++++++++-
> include/linux/perf/riscv_pmu.h | 10 +-
> include/linux/perf_event.h | 3 +-
> tools/lib/perf/mmap.c | 65 +++++++
> tools/perf/tests/mmap-basic.c | 4 +-
> 10 files changed, 435 insertions(+), 21 deletions(-)
> create mode 100644 arch/riscv/kernel/perf_event.c
It looks like there's a handful of outstanding review comments, so I'm
going to mark this as changes requested in patchwork -- sorry if I
missed a v3.
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