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Message-ID: <20230621235508.113949-7-suravee.suthikulpanit@amd.com>
Date: Wed, 21 Jun 2023 18:54:53 -0500
From: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
To: <linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
<kvm@...r.kernel.org>
CC: <joro@...tes.org>, <robin.murphy@....com>, <yi.l.liu@...el.com>,
<alex.williamson@...hat.com>, <jgg@...dia.com>,
<nicolinc@...dia.com>, <baolu.lu@...ux.intel.com>,
<eric.auger@...hat.com>, <pandoh@...gle.com>,
<kumaranand@...gle.com>, <jon.grimm@....com>,
<santosh.shukla@....com>, <vasant.hegde@....com>,
<jay.chen@....com>, <joseph.chung@....com>,
"Suravee Suthikulpanit" <suravee.suthikulpanit@....com>
Subject: [RFC PATCH 06/21] iommu/amd: Modify set_dte_entry() to add gcr3 input parameter
To preparation for subsequent changes. There is no functional change.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 10 ++++++----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 5d2eed07a1fa..dbfc70556220 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -16,6 +16,7 @@ extern void iommu_feature_disable(struct amd_iommu *iommu, u8 bit);
extern u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end);
extern void set_dte_entry(struct amd_iommu *iommu, u16 devid,
struct protection_domain *domain,
+ u64 *gcr3_tbl,
bool ats, bool ppr);
extern int iommu_flush_dte(struct amd_iommu *iommu, u16 devid);
extern struct protection_domain *to_pdomain(struct iommu_domain *dom);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 3b31ecde0122..4728929657f5 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1590,7 +1590,9 @@ static void set_dte_entry_v2(struct amd_iommu *iommu,
}
void set_dte_entry(struct amd_iommu *iommu, u16 devid,
- struct protection_domain *domain, bool ats, bool ppr)
+ struct protection_domain *domain,
+ u64 *gcr3_tbl,
+ bool ats, bool ppr)
{
u64 pte_root = 0;
u64 flags = 0;
@@ -1622,7 +1624,7 @@ void set_dte_entry(struct amd_iommu *iommu, u16 devid,
pte_root |= 1ULL << DEV_ENTRY_PPR;
}
- set_dte_entry_v2(iommu, domain, domain->gcr3_tbl, &pte_root, &flags);
+ set_dte_entry_v2(iommu, domain, gcr3_tbl, &pte_root, &flags);
if ((domain->flags & PD_IOMMUV2_MASK) &&
amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) {
@@ -1686,7 +1688,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
domain->dev_cnt += 1;
/* Update device table */
- set_dte_entry(iommu, dev_data->devid, domain,
+ set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl,
ats, dev_data->iommu_v2);
clone_aliases(iommu, dev_data->dev);
@@ -1965,7 +1967,7 @@ static void update_device_table(struct protection_domain *domain)
if (!iommu)
continue;
- set_dte_entry(iommu, dev_data->devid, domain,
+ set_dte_entry(iommu, dev_data->devid, domain, domain->gcr3_tbl,
dev_data->ats.enabled, dev_data->iommu_v2);
clone_aliases(iommu, dev_data->dev);
}
--
2.34.1
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