linux-kernel - Re: [PATCH v3 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

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Message-ID: <4bed9d52-6729-6e0d-5267-17d8f6eb892a@starfivetech.com>
Date:   Wed, 21 Jun 2023 14:04:56 +0800
From:   William Qiu <william.qiu@...rfivetech.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <devicetree@...r.kernel.org>, <linux-spi@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
CC:     Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Emil Renner Berthing <kernel@...il.dk>,
        Ziv Xu <ziv.xu@...rfivetech.com>
Subject: Re: [PATCH v3 3/3] riscv: dts: starfive: Add QSPI controller node for
 StarFive JH7110 SoC



On 2023/6/19 20:20, Krzysztof Kozlowski wrote:
> On 19/06/2023 10:35, William Qiu wrote:
>> Add the quad spi controller node for the StarFive JH7110 SoC.
>> 
>> Co-developed-by: Ziv Xu <ziv.xu@...rfivetech.com>
>> Signed-off-by: Ziv Xu <ziv.xu@...rfivetech.com>
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
>> ---
>>  .../jh7110-starfive-visionfive-2.dtsi         | 32 +++++++++++++++++++
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 18 +++++++++++
>>  2 files changed, 50 insertions(+)
>> 
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..22212c1150f9 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -126,6 +126,38 @@ &i2c6 {
>>  	status = "okay";
>>  };
>>  
>> +&qspi {
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +
>> +	nor_flash: flash@0 {
>> +		compatible = "jedec,spi-nor";
>> +		reg=<0>;
> 
> Missing spaces.
> 
Will fix.
>> +		cdns,read-delay = <5>;
>> +		spi-max-frequency = <12000000>;
>> +		cdns,tshsl-ns = <1>;
>> +		cdns,tsd2d-ns = <1>;
>> +		cdns,tchsh-ns = <1>;
>> +		cdns,tslch-ns = <1>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			spl@0 {
>> +				reg = <0x0 0x20000>;
>> +			};
>> +			uboot@...000 {
>> +				reg = <0x100000 0x300000>;
>> +			};
>> +			data@...000 {
>> +				reg = <0xf00000 0x100000>;
>> +			};
>> +		};
>> +	};
>> +};
>> +
>>  &sysgpio {
>>  	i2c0_pins: i2c0-0 {
>>  		i2c-pins {
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 4c5fdb905da8..0b24f9e66e67 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -440,6 +440,24 @@ i2c6: i2c@...60000 {
>>  			status = "disabled";
>>  		};
>>  
>> +		qspi: spi@...10000 {
>> +			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
>> +			reg = <0x0 0x13010000 0x0 0x10000
>> +				0x0 0x21000000 0x0 0x400000>;
> 
> This should be two items so <>, <>. Not one item.
> 
> Best regards,
> Krzysztof
> 
Will fix.
Thanks for taking time to review this patch series.

Best reagards
William