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Date:   Thu, 22 Jun 2023 15:53:09 -0700
From:   Dave Jiang <dave.jiang@...el.com>
To:     Terry Bowman <terry.bowman@....com>, <alison.schofield@...el.com>,
        <vishal.l.verma@...el.com>, <ira.weiny@...el.com>,
        <bwidawsk@...nel.org>, <dan.j.williams@...el.com>,
        <Jonathan.Cameron@...wei.com>, <linux-cxl@...r.kernel.org>
CC:     <rrichter@....com>, <linux-kernel@...r.kernel.org>,
        <bhelgaas@...gle.com>
Subject: Re: [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to
 @dport_dev



On 6/21/23 20:51, Terry Bowman wrote:
> From: Robert Richter <rrichter@....com>
> 
> Reading code like dport->dport does not immediately suggest that this
> points to the corresponding device structure of the dport. Rename
> struct member @dport to @dport_dev.
> 
> While at it, also rename @new argument of add_dport() to @dport. This
> better describes the variable as a dport (e.g. new->dport becomes to
> dport->dport_dev).
> 
> Co-developed-by: Terry Bowman <terry.bowman@....com>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
> Signed-off-by: Robert Richter <rrichter@....com>

Reviewed-by: Dave Jiang <dave.jiang@...el.com>

> ---
>   drivers/cxl/core/port.c   | 20 ++++++++++----------
>   drivers/cxl/core/region.c |  4 ++--
>   drivers/cxl/cxl.h         |  4 ++--
>   3 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 76888c75dae4..7d3079f5b7b5 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -605,7 +605,7 @@ static int devm_cxl_link_parent_dport(struct device *host,
>   	if (!parent_dport)
>   		return 0;
>   
> -	rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport->kobj,
> +	rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport_dev->kobj,
>   			       "parent_dport");
>   	if (rc)
>   		return rc;
> @@ -658,7 +658,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
>   		if (iter->host_bridge)
>   			port->host_bridge = iter->host_bridge;
>   		else if (parent_dport->rch)
> -			port->host_bridge = parent_dport->dport;
> +			port->host_bridge = parent_dport->dport_dev;
>   		else
>   			port->host_bridge = iter->uport;
>   		dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge));
> @@ -847,22 +847,22 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id)
>   	return NULL;
>   }
>   
> -static int add_dport(struct cxl_port *port, struct cxl_dport *new)
> +static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
>   {
>   	struct cxl_dport *dup;
>   	int rc;
>   
>   	device_lock_assert(&port->dev);
> -	dup = find_dport(port, new->port_id);
> +	dup = find_dport(port, dport->port_id);
>   	if (dup) {
>   		dev_err(&port->dev,
>   			"unable to add dport%d-%s non-unique port id (%s)\n",
> -			new->port_id, dev_name(new->dport),
> -			dev_name(dup->dport));
> +			dport->port_id, dev_name(dport->dport_dev),
> +			dev_name(dup->dport_dev));
>   		return -EBUSY;
>   	}
>   
> -	rc = xa_insert(&port->dports, (unsigned long)new->dport, new,
> +	rc = xa_insert(&port->dports, (unsigned long)dport->dport_dev, dport,
>   		       GFP_KERNEL);
>   	if (rc)
>   		return rc;
> @@ -895,8 +895,8 @@ static void cxl_dport_remove(void *data)
>   	struct cxl_dport *dport = data;
>   	struct cxl_port *port = dport->port;
>   
> -	xa_erase(&port->dports, (unsigned long) dport->dport);
> -	put_device(dport->dport);
> +	xa_erase(&port->dports, (unsigned long) dport->dport_dev);
> +	put_device(dport->dport_dev);
>   }
>   
>   static void cxl_dport_unlink(void *data)
> @@ -954,7 +954,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>   		dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
>   			&component_reg_phys);
>   
> -	dport->dport = dport_dev;
> +	dport->dport_dev = dport_dev;
>   	dport->port_id = port_id;
>   	dport->component_reg_phys = component_reg_phys;
>   	dport->port = port;
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index f822de44bee0..13cda989d944 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1162,7 +1162,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
>   			dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n",
>   				dev_name(port->uport), dev_name(&port->dev),
>   				dev_name(&cxlsd->cxld.dev),
> -				dev_name(ep->dport->dport),
> +				dev_name(ep->dport->dport_dev),
>   				cxl_rr->nr_targets_set);
>   			return -ENXIO;
>   		}
> @@ -1173,7 +1173,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
>   	cxl_rr->nr_targets_set += inc;
>   	dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n",
>   		dev_name(port->uport), dev_name(&port->dev),
> -		cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport),
> +		cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev),
>   		dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos);
>   
>   	return 0;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 7c8674079f1a..7232c2a0e27c 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -589,7 +589,7 @@ struct cxl_rcrb_info {
>   
>   /**
>    * struct cxl_dport - CXL downstream port
> - * @dport: PCI bridge or firmware device representing the downstream link
> + * @dport_dev: PCI bridge or firmware device representing the downstream link
>    * @port_id: unique hardware identifier for dport in decoder target list
>    * @component_reg_phys: downstream port component registers
>    * @rcrb: Data about the Root Complex Register Block layout
> @@ -597,7 +597,7 @@ struct cxl_rcrb_info {
>    * @port: reference to cxl_port that contains this downstream port
>    */
>   struct cxl_dport {
> -	struct device *dport;
> +	struct device *dport_dev;
>   	int port_id;
>   	resource_size_t component_reg_phys;
>   	struct cxl_rcrb_info rcrb;

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