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Message-ID: <2d063e49-8d58-08ff-c2d3-1f27a9576a68@intel.com>
Date: Thu, 22 Jun 2023 16:14:42 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Terry Bowman <terry.bowman@....com>, <alison.schofield@...el.com>,
<vishal.l.verma@...el.com>, <ira.weiny@...el.com>,
<bwidawsk@...nel.org>, <dan.j.williams@...el.com>,
<Jonathan.Cameron@...wei.com>, <linux-cxl@...r.kernel.org>
CC: <rrichter@....com>, <linux-kernel@...r.kernel.org>,
<bhelgaas@...gle.com>
Subject: Re: [PATCH v6 08/27] cxl/pci: Refactor component register discovery
for reuse
On 6/21/23 20:51, Terry Bowman wrote:
> The endpoint implements component register setup code. Refactor it for
> reuse with RCRB, downstream port, and upstream port setup.
>
> Move PCI specifics from cxl_setup_regs() into cxl_pci_setup_regs().
>
> Move cxl_setup_regs() into cxl/core/regs.c and export it. This also
> includes supporting static functions cxl_map_registerblock(),
> cxl_unmap_register_block() and cxl_probe_regs().
>
> Co-developed-by: Robert Richter <rrichter@....com>
> Signed-off-by: Robert Richter <rrichter@....com>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> ---
> drivers/cxl/core/regs.c | 77 +++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 1 +
> drivers/cxl/pci.c | 79 +++--------------------------------------
> 3 files changed, 83 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 713e4a9ca35a..e035ad8827a4 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -338,6 +338,83 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> }
> EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
>
> +static int cxl_map_regblock(struct cxl_register_map *map)
> +{
> + struct device *dev = map->dev;
> +
> + map->base = ioremap(map->resource, map->max_size);
> + if (!map->base) {
> + dev_err(dev, "failed to map registers\n");
> + return -ENOMEM;
> + }
> +
> + dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> + return 0;
> +}
> +
> +static void cxl_unmap_regblock(struct cxl_register_map *map)
> +{
> + iounmap(map->base);
> + map->base = NULL;
> +}
> +
> +static int cxl_probe_regs(struct cxl_register_map *map)
> +{
> + struct cxl_component_reg_map *comp_map;
> + struct cxl_device_reg_map *dev_map;
> + struct device *dev = map->dev;
> + void __iomem *base = map->base;
> +
> + switch (map->reg_type) {
> + case CXL_REGLOC_RBI_COMPONENT:
> + comp_map = &map->component_map;
> + cxl_probe_component_regs(dev, base, comp_map);
> + if (!comp_map->hdm_decoder.valid) {
> + dev_err(dev, "HDM decoder registers not found\n");
> + return -ENXIO;
> + }
> +
> + if (!comp_map->ras.valid)
> + dev_dbg(dev, "RAS registers not found\n");
> +
> + dev_dbg(dev, "Set up component registers\n");
> + break;
> + case CXL_REGLOC_RBI_MEMDEV:
> + dev_map = &map->device_map;
> + cxl_probe_device_regs(dev, base, dev_map);
> + if (!dev_map->status.valid || !dev_map->mbox.valid ||
> + !dev_map->memdev.valid) {
> + dev_err(dev, "registers not found: %s%s%s\n",
> + !dev_map->status.valid ? "status " : "",
> + !dev_map->mbox.valid ? "mbox " : "",
> + !dev_map->memdev.valid ? "memdev " : "");
> + return -ENXIO;
> + }
> +
> + dev_dbg(dev, "Probing device registers...\n");
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +int cxl_setup_regs(struct cxl_register_map *map)
> +{
> + int rc;
> +
> + rc = cxl_map_regblock(map);
> + if (rc)
> + return rc;
> +
> + rc = cxl_probe_regs(map);
> + cxl_unmap_regblock(map);
> +
> + return rc;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
> +
> resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
> enum cxl_rcrb which)
> {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index bd68d5fabf21..ae265357170e 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -264,6 +264,7 @@ int cxl_map_device_regs(struct cxl_register_map *map,
> enum cxl_regloc_type;
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> struct cxl_register_map *map);
> +int cxl_setup_regs(struct cxl_register_map *map);
> struct cxl_dport;
> resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
> struct cxl_dport *dport);
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 0a89b96e6a8d..ac17bc0430dc 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -274,70 +274,8 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
> return 0;
> }
>
> -static int cxl_map_regblock(struct cxl_register_map *map)
> -{
> - struct device *dev = map->dev;
> -
> - map->base = ioremap(map->resource, map->max_size);
> - if (!map->base) {
> - dev_err(dev, "failed to map registers\n");
> - return -ENOMEM;
> - }
> -
> - dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
> - return 0;
> -}
> -
> -static void cxl_unmap_regblock(struct cxl_register_map *map)
> -{
> - iounmap(map->base);
> - map->base = NULL;
> -}
> -
> -static int cxl_probe_regs(struct cxl_register_map *map)
> -{
> - struct cxl_component_reg_map *comp_map;
> - struct cxl_device_reg_map *dev_map;
> - struct device *dev = map->dev;
> - void __iomem *base = map->base;
> -
> - switch (map->reg_type) {
> - case CXL_REGLOC_RBI_COMPONENT:
> - comp_map = &map->component_map;
> - cxl_probe_component_regs(dev, base, comp_map);
> - if (!comp_map->hdm_decoder.valid) {
> - dev_err(dev, "HDM decoder registers not found\n");
> - return -ENXIO;
> - }
> -
> - if (!comp_map->ras.valid)
> - dev_dbg(dev, "RAS registers not found\n");
> -
> - dev_dbg(dev, "Set up component registers\n");
> - break;
> - case CXL_REGLOC_RBI_MEMDEV:
> - dev_map = &map->device_map;
> - cxl_probe_device_regs(dev, base, dev_map);
> - if (!dev_map->status.valid || !dev_map->mbox.valid ||
> - !dev_map->memdev.valid) {
> - dev_err(dev, "registers not found: %s%s%s\n",
> - !dev_map->status.valid ? "status " : "",
> - !dev_map->mbox.valid ? "mbox " : "",
> - !dev_map->memdev.valid ? "memdev " : "");
> - return -ENXIO;
> - }
> -
> - dev_dbg(dev, "Probing device registers...\n");
> - break;
> - default:
> - break;
> - }
> -
> - return 0;
> -}
> -
> -static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map)
> +static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> + struct cxl_register_map *map)
> {
> int rc;
>
> @@ -345,14 +283,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> if (rc)
> return rc;
>
> - rc = cxl_map_regblock(map);
> - if (rc)
> - return rc;
> -
> - rc = cxl_probe_regs(map);
> - cxl_unmap_regblock(map);
> -
> - return rc;
> + return cxl_setup_regs(map);
> }
>
> /*
> @@ -683,7 +614,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> dev_warn(&pdev->dev,
> "Device DVSEC not present, skip CXL.mem init\n");
>
> - rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
> if (rc)
> return rc;
>
> @@ -696,7 +627,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> * still be useful for management functions so don't return an error.
> */
> cxlds->component_reg_phys = CXL_RESOURCE_NONE;
> - rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> if (rc)
> dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
>
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