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Message-ID: <51c2d17bc73d1b5ddd62f4022966ff48a511d6ab.1687414716.git.quic_varada@quicinc.com>
Date: Thu, 22 Jun 2023 11:52:10 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <vkoul@...nel.org>,
<kishon@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<gregkh@...uxfoundation.org>, <catalin.marinas@....com>,
<will@...nel.org>, <p.zabel@...gutronix.de>, <arnd@...db.de>,
<geert+renesas@...der.be>, <neil.armstrong@...aro.org>,
<nfraprado@...labora.com>, <broonie@...nel.org>,
<rafal@...ecki.pl>, <quic_srichara@...cinc.com>,
<quic_varada@...cinc.org>, <quic_wcheng@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-usb@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>
CC: Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: [PATCH v2 3/6] phy: qcom-m31: Introduce qcom,m31 USB phy driver
Add the M31 USB2 phy driver.
Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
---
v1:
Combine driver, makefile and kconfig into 1 patch
Remove 'qscratch' region and its usage. The controller driver takes care
of those settings
Use compatible/data to handle ipq5332 init
Drop the default case
Get resources by index instead of name as there is only one resource
Add clock
Fix other review comments in the driver
---
drivers/phy/qualcomm/Kconfig | 11 ++
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-m31.c | 256 ++++++++++++++++++++++++++++++++++++
3 files changed, 268 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 67a45d9..8a363dd 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -188,3 +188,14 @@ config PHY_QCOM_IPQ806X_USB
This option enables support for the Synopsis PHYs present inside the
Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
both HS and SS PHY controllers.
+
+config PHY_QCOM_M31_USB
+ tristate "Qualcomm M31 HS PHY driver support"
+ depends on (USB || USB_GADGET) && ARCH_QCOM
+ select USB_PHY
+ help
+ Enable this to support M31 HS PHY transceivers on Qualcomm chips
+ with DWC3 USB core. It handles PHY initialization, clock
+ management required after resetting the hardware and power
+ management. This driver is required even for peripheral only or
+ host only mode configurations.
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index de3dc9c..79a6e75 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
+obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
new file mode 100644
index 0000000..8700728
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/usb/of.h>
+#include <linux/usb/phy.h>
+
+enum clk_reset_action {
+ CLK_RESET_DEASSERT = 0,
+ CLK_RESET_ASSERT = 1
+};
+
+
+#define USB2PHY_PORT_UTMI_CTRL1 0x40
+
+#define USB2PHY_PORT_UTMI_CTRL2 0x44
+ #define UTMI_ULPI_SEL BIT(7)
+ #define UTMI_TEST_MUX_SEL BIT(6)
+
+#define HS_PHY_CTRL_REG 0x10
+ #define UTMI_OTG_VBUS_VALID BIT(20)
+ #define SW_SESSVLD_SEL BIT(28)
+
+#define USB_PHY_UTMI_CTRL0 0x3c
+
+#define USB_PHY_UTMI_CTRL5 0x50
+ #define POR_EN BIT(1)
+ #define ATERESET ~BIT(0)
+
+#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
+ #define COMMONONN BIT(7)
+ #define FSEL BIT(4)
+ #define RETENABLEN BIT(3)
+ #define FREQ_24MHZ (5 << 4)
+
+#define USB_PHY_HS_PHY_CTRL2 0x64
+ #define USB2_SUSPEND_N_SEL BIT(3)
+ #define USB2_SUSPEND_N BIT(2)
+ #define USB2_UTMI_CLK_EN BIT(1)
+
+#define USB_PHY_CFG0 0x94
+ #define UTMI_PHY_OVERRIDE_EN BIT(1)
+
+#define USB_PHY_REFCLK_CTRL 0xa0
+ #define CLKCORE BIT(1)
+
+#define USB2PHY_PORT_POWERDOWN 0xa4
+ #define POWER_UP BIT(0)
+ #define POWER_DOWN 0
+
+#define USB_PHY_FSEL_SEL 0xb8
+ #define FREQ_SEL BIT(0)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc
+ #define USB2_0_TX_ENABLE BIT(2)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
+ #define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
+ #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
+ #define ODT_VALUE_38_02_OHM GENMASK(7, 6)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
+ #define ODT_VALUE_45_02_OHM BIT(2)
+ #define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
+
+#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
+ #define XCFG_COARSE_TUNE_NUM BIT(1)
+ #define XCFG_FINE_TUNE_NUM BIT(3)
+
+struct m31_phy_regs {
+ u32 off;
+ u32 val;
+ u32 delay;
+};
+
+struct m31_priv_data {
+ bool ulpi_mode;
+ const struct m31_phy_regs *regs;
+};
+
+#define M31_REG(__o, __v, __d) \
+ { .off = __o, .val = __v, .delay = __d }
+
+#define M31_REG_INVALID 0xffffffffu
+
+struct m31_phy_regs m31_ipq5332_regs[] = {
+ M31_REG(USB_PHY_CFG0, UTMI_PHY_OVERRIDE_EN, 0),
+ M31_REG(USB_PHY_UTMI_CTRL5, POR_EN, 15),
+ M31_REG(USB_PHY_FSEL_SEL, FREQ_SEL, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL_COMMON0,
+ COMMONONN | FREQ_24MHZ | RETENABLEN, 0),
+ M31_REG(USB_PHY_UTMI_CTRL5, POR_EN & ATERESET, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_11,
+ XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_4,
+ HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA |
+ ODT_VALUE_38_02_OHM, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_1, USB2_0_TX_ENABLE, 0),
+ M31_REG(USB2PHY_USB_PHY_M31_XCFGI_5,
+ ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA, 4),
+ M31_REG(USB_PHY_UTMI_CTRL5, 0x0, 0),
+ M31_REG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0),
+ M31_REG(M31_REG_INVALID, 0, 0),
+};
+
+struct m31usb_phy {
+ struct usb_phy phy;
+ void __iomem *base;
+ const struct m31_phy_regs *regs;
+
+ struct clk *cfg_ahb_clk;
+ struct reset_control *phy_reset;
+
+ bool cable_connected;
+ bool suspended;
+ bool ulpi_mode;
+};
+
+static void m31usb_phy_enable_clock(struct m31usb_phy *qphy)
+{
+ const struct m31_phy_regs *regs = qphy->regs;
+
+ for (; regs->off != M31_REG_INVALID; regs++) {
+ writel(regs->val, qphy->base + regs->off);
+ if (regs->delay)
+ udelay(regs->delay);
+ }
+}
+
+static int m31usb_phy_init(struct usb_phy *phy)
+{
+ int ret;
+ struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy);
+
+ ret = clk_prepare_enable(qphy->cfg_ahb_clk);
+ if (ret) {
+ dev_err(phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
+ return ret;
+ }
+
+ /* Perform phy reset */
+ reset_control_assert(qphy->phy_reset);
+ udelay(5);
+ reset_control_deassert(qphy->phy_reset);
+
+ /* configure for ULPI mode if requested */
+ if (qphy->ulpi_mode)
+ writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2);
+
+ /* Enable the PHY */
+ writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN);
+
+ /* Make sure above write completed */
+ wmb();
+
+ /* Turn on phy ref clock */
+ m31usb_phy_enable_clock(qphy);
+
+ return 0;
+}
+
+static void m31usb_phy_shutdown(struct usb_phy *phy)
+{
+ struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy);
+
+ /* Disable the PHY */
+ writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN);
+ /* Make sure above write completed */
+ wmb();
+
+ clk_disable_unprepare(qphy->cfg_ahb_clk);
+}
+
+static int m31usb_phy_probe(struct platform_device *pdev)
+{
+ const struct m31_priv_data *data;
+ struct device *dev = &pdev->dev;
+ struct m31usb_phy *qphy;
+ int ret;
+
+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
+ if (!qphy)
+ return -ENOMEM;
+
+ qphy->phy.dev = dev;
+
+ qphy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(qphy->base))
+ return PTR_ERR(qphy->base);
+
+ qphy->phy_reset = devm_reset_control_get_exclusive_by_index(dev, 0);
+ if (IS_ERR(qphy->phy_reset))
+ return PTR_ERR(qphy->phy_reset);
+
+ qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
+ platform_set_drvdata(pdev, qphy);
+
+ data = of_device_get_match_data(dev);
+ qphy->regs = data->regs;
+ qphy->ulpi_mode = data->ulpi_mode;
+
+ qphy->phy.label = "m31-usb-phy";
+ qphy->phy.init = m31usb_phy_init;
+ qphy->phy.shutdown = m31usb_phy_shutdown;
+ qphy->phy.type = USB_PHY_TYPE_USB2;
+
+ ret = usb_add_phy_dev(&qphy->phy);
+
+ return ret;
+}
+
+static void m31usb_phy_remove(struct platform_device *pdev)
+{
+ struct m31usb_phy *qphy = platform_get_drvdata(pdev);
+
+ usb_remove_phy(&qphy->phy);
+}
+
+struct m31_priv_data m31_ipq5332_data = {
+ .ulpi_mode = false,
+ .regs = m31_ipq5332_regs,
+};
+
+static const struct of_device_id m31usb_phy_id_table[] = {
+ { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, m31usb_phy_id_table);
+
+static struct platform_driver m31usb_phy_driver = {
+ .probe = m31usb_phy_probe,
+ .remove_new = m31usb_phy_remove,
+ .driver = {
+ .name = "qcom-m31usb-phy",
+ .of_match_table = m31usb_phy_id_table,
+ },
+};
+
+module_platform_driver(m31usb_phy_driver);
+
+MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver");
+MODULE_LICENSE("GPL");
--
2.7.4
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