linux-kernel - RE: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes

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Message-ID: <SJ0PR12MB5676D09F6B1D2600AFFBFA8FA022A@SJ0PR12MB5676.namprd12.prod.outlook.com>
Date:   Thu, 22 Jun 2023 10:17:46 +0000
From:   Besar Wicaksono <bwicaksono@...dia.com>
To:     Ilkka Koskinen <ilkka@...amperecomputing.com>,
        Will Deacon <will@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Mark Rutland <mark.rutland@....com>
CC:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes



> -----Original Message-----
> From: Ilkka Koskinen <ilkka@...amperecomputing.com>
> Sent: Thursday, June 22, 2023 8:12 AM
> To: Will Deacon <will@...nel.org>; Robin Murphy <robin.murphy@....com>;
> Besar Wicaksono <bwicaksono@...dia.com>; Suzuki K Poulose
> <suzuki.poulose@....com>; Mark Rutland <mark.rutland@....com>
> Cc: Ilkka Koskinen <ilkka@...amperecomputing.com>; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org
> Subject: [PATCH 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
> 
> External email: Use caution opening links or attachments
> 
> 
> Split the 64-bit register accesses if 64-bit access is not supported
> by the PMU.
> 
> Signed-off-by: Ilkka Koskinen <ilkka@...amperecomputing.com>

Reviewed-by: Besar Wicaksono <bwicaksono@...dia.com>

Thanks,
Besar

> ---
>  drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c
> b/drivers/perf/arm_cspmu/arm_cspmu.c
> index e2b7827c4563..0f517152cb4e 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -696,7 +696,10 @@ static void arm_cspmu_write_counter(struct
> perf_event *event, u64 val)
>         if (use_64b_counter_reg(cspmu)) {
>                 offset = counter_offset(sizeof(u64), event->hw.idx);
> 
> -               writeq(val, cspmu->base1 + offset);
> +               if (cspmu->has_atomic_dword)
> +                       writeq(val, cspmu->base1 + offset);
> +               else
> +                       lo_hi_writeq(val, cspmu->base1 + offset);
>         } else {
>                 offset = counter_offset(sizeof(u32), event->hw.idx);
> 
> --
> 2.40.1