[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZJYjOor3TKSeIo7F@nvidia.com>
Date: Fri, 23 Jun 2023 19:56:58 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: "Suthikulpanit, Suravee" <suravee.suthikulpanit@....com>
Cc: linux-kernel@...r.kernel.org, iommu@...ts.linux.dev,
kvm@...r.kernel.org, joro@...tes.org, robin.murphy@....com,
yi.l.liu@...el.com, alex.williamson@...hat.com,
nicolinc@...dia.com, baolu.lu@...ux.intel.com,
eric.auger@...hat.com, pandoh@...gle.com, kumaranand@...gle.com,
jon.grimm@....com, santosh.shukla@....com, vasant.hegde@....com,
jay.chen@....com, joseph.chung@....com
Subject: Re: [RFC PATCH 00/21] iommu/amd: Introduce support for HW
accelerated vIOMMU w/ nested page table
On Fri, Jun 23, 2023 at 03:05:06PM -0700, Suthikulpanit, Suravee wrote:
> For example, an AMD IOMMU hardware is normally listed as a PCI device (e.g.
> PCI ID 00:00.2). To setup IOMMU PAS for this IOMMU instance, the IOMMU
> driver allocate an IOMMU v1 page table for this device, which contains PAS
> mapping.
So it is just system dram?
> The IOMMU hardware use the PAS for storing Guest IOMMU information such as
> Guest MMIOs, DevID Mapping Table, DomID Mapping Table, and Guest
> Command/Event/PPR logs.
Why does it have to be in kernel memory?
Why not store the whole thing in user mapped memory and have the VMM
manipulate it directly?
Jason
Powered by blists - more mailing lists