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Message-ID: <ZJWdbbNESp1+6GVN@nvidia.com>
Date: Fri, 23 Jun 2023 10:26:05 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: ankita@...dia.com
Cc: alex.williamson@...hat.com, aniketa@...dia.com, cjia@...dia.com,
kwankhede@...dia.com, targupta@...dia.com, vsethi@...dia.com,
acurrid@...dia.com, apopple@...dia.com, jhubbard@...dia.com,
danw@...dia.com, kvm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/1] vfio/nvgpu: Add vfio pci variant module for grace
hopper
On Wed, Jun 21, 2023 at 08:07:20PM -0700, ankita@...dia.com wrote:
> + if (caps.size) {
> + info.flags |= VFIO_REGION_INFO_FLAG_CAPS;
> + if (info.argsz < sizeof(info) + caps.size) {
> + info.argsz = sizeof(info) + caps.size;
> + info.cap_offset = 0;
Shouldn't this be an error if we can't fit the caps into the response?
Silently discarding the caps seems wrong..
> +static ssize_t nvgpu_vfio_pci_read(struct vfio_device *core_vdev,
> + char __user *buf, size_t count, loff_t *ppos)
> +{
> + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
> +
> + /*
> + * Only the device memory present on the hardware is mapped, which may
> + * not be power-of-2 aligned. A read to the BAR2 region implies an
> + * access outside the available device memory on the hardware.
> + */
> + if (index == VFIO_PCI_BAR2_REGION_INDEX)
> + return -EINVAL;
What does the qemu do in this case? Crash the VM?
Jason
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