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Message-Id: <20230623134351.1898379-4-kernel@xen0n.name>
Date: Fri, 23 Jun 2023 21:43:45 +0800
From: WANG Xuerui <kernel@...0n.name>
To: Huacai Chen <chenhuacai@...nel.org>
Cc: WANG Rui <wangrui@...ngson.cn>, Xi Ruoyao <xry111@...111.site>,
loongarch@...ts.linux.dev, linux-kbuild@...r.kernel.org,
llvm@...ts.linux.dev, linux-kernel@...r.kernel.org,
WANG Xuerui <git@...0n.name>
Subject: [PATCH 3/9] LoongArch: Prepare for assemblers with proper FCSR bank support
From: WANG Xuerui <git@...0n.name>
The GNU assembler (as of 2.40) mis-treats FCSR operands as GPRs, but
the LLVM IAS does not. Probe for this and refer to FCSRs as "$fcsrNN"
if support is present.
Signed-off-by: WANG Xuerui <git@...0n.name>
---
arch/loongarch/Kconfig | 3 +++
arch/loongarch/include/asm/fpregdef.h | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 743d87655742..c8e4f8b03c55 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -242,6 +242,9 @@ config SCHED_OMIT_FRAME_POINTER
config AS_HAS_EXPLICIT_RELOCS
def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))
+config AS_HAS_FCSR_BANK
+ def_bool $(as-instr,x:movfcsr2gr \$t0$(comma)\$fcsr0)
+
config CC_HAS_LSX_EXTENSION
def_bool $(cc-option,-mlsx)
diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h
index b6be527831dd..b0ac640db74c 100644
--- a/arch/loongarch/include/asm/fpregdef.h
+++ b/arch/loongarch/include/asm/fpregdef.h
@@ -40,6 +40,12 @@
#define fs6 $f30
#define fs7 $f31
+#ifdef CONFIG_AS_HAS_FCSR_BANK
+#define fcsr0 $fcsr0
+#define fcsr1 $fcsr1
+#define fcsr2 $fcsr2
+#define fcsr3 $fcsr3
+#else
/*
* Current binutils expects *GPRs* at FCSR position for the FCSR
* operation instructions, so define aliases for those used.
@@ -48,5 +54,6 @@
#define fcsr1 $r1
#define fcsr2 $r2
#define fcsr3 $r3
+#endif
#endif /* _ASM_FPREGDEF_H */
--
2.40.0
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